Invention Application
WO2018063228A1 METHODS OF UTILIZING LOW TEMPERATURE SOLDER ASSISTED MOUNTING TECHNIQUES FOR PACKAGE STRUCTURES
审中-公开
利用低温焊剂辅助安装技术进行封装结构的方法
- Patent Title: METHODS OF UTILIZING LOW TEMPERATURE SOLDER ASSISTED MOUNTING TECHNIQUES FOR PACKAGE STRUCTURES
- Patent Title (中): 利用低温焊剂辅助安装技术进行封装结构的方法
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Application No.: PCT/US2016/054381Application Date: 2016-09-29
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Publication No.: WO2018063228A1Publication Date: 2018-04-05
- Inventor: KARHADE, Omkar G. , RARAVIKAR, Nachiket R. , SANE, Sandeep B.
- Applicant: INTEL CORPORATION
- Applicant Address: 2200 Mission College Boulevard Santa Clara, California 95054 US
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: 2200 Mission College Boulevard Santa Clara, California 95054 US
- Agency: ORTIZ, Kathy J.
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/488 ; H01L21/324 ; H01L23/12
Abstract:
Methods/structures of joining package structures are described. Those methods/structures may include a device disposed on first side of substrate and an array of conductive interconnect structures disposed on a second side of the first substrate. The conductive interconnect structures of the array may comprise a solder material, wherein the solder material comprises a low temperature alloying element concentration of less than about 5 percent. A second substrate is coupled to the array of conductive interconnect structures.
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