Invention Application
- Patent Title: DATA BIT INVERSION TRACKING IN CACHE MEMORY TO REDUCE DATA BITS WRITTEN FOR WRITE OPERATIONS
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Application No.: PCT/US2018/045379Application Date: 2018-08-06
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Publication No.: WO2019032455A1Publication Date: 2019-02-14
- Inventor: SHIN, Hyunsuk , KIM, Jung Pill , KIM, Sungryul
- Applicant: QUALCOMM INCORPORATED
- Applicant Address: ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714 US
- Assignee: QUALCOMM INCORPORATED
- Current Assignee: QUALCOMM INCORPORATED
- Current Assignee Address: ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714 US
- Agency: TERRANOVA, Steven, N.
- Priority: US15/672,992 20170809
- Main IPC: G06F12/0804
- IPC: G06F12/0804 ; G06F12/0891 ; G11C7/10 ; G11C11/4063
Abstract:
Data bit inversion tracking in cache memory to reduce data bits written for write operations is disclosed. In one aspect, a cache memory including a cache controller and a cache array is provided. The cache array includes one or more cache entries, each of which includes a cache data field and a bit change track field. The cache controller compares a current cache data word to a new data word to be written and stores a bit track change word representing the difference (i.e., inverted bits) between the current cache data word and the new data word in the bit change track field. By using the bit track change word stored in the bit change track field to determine whether fewer bit writes are required to write data in an inverted or a non-inverted form, power consumption can be reduced for write operations through reduced bit write operations.
Information query
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