公开(公告)号：WO2021154325A1

公开(公告)日：2021-08-05

申请号：PCT/US2020/035132

申请日：2020-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： KIM, Jee-Yeon ,  MIZUTANI, Yuki ,  TOYAMA, Fumiaki

IPC: H01L27/11551 ,  H01L27/11524 ,  G11C16/06 ,  G11C11/4063

Abstract: A bonded assembly includes a memory die containing a memory device and a plurality of bit lines, and logic die bonded to the memory die. The logic die contains a control circuit configured to control operation of the memory device. The control circuit contains a peripheral circuit region, a sense amplifier region, and a power and control signal region located adjacent to the sense amplifier region and containing at least one power and control signal interconnect structure which is configured to provide a power or control signal to or from the peripheral circuit region.

公开(公告)号：WO2021041390A1

公开(公告)日：2021-03-04

申请号：PCT/US2020/047764

申请日：2020-08-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MURPHY, Richard C. ,  HUSH, Glen E. ,  SUN, Honglin

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08 ,  G11C11/406 ,  G11C11/4063

Abstract: Devices and methods related to spiking neural units in memory. One device includes a memory array and a complementary metal-oxide semiconductor (CMOS) coupled to the memory array and located under the memory array, wherein the CMOS includes a spiking neural unit comprising logic configured to receive an input to increase a weight stored in a memory cell of the memory array, collect the weight from the memory cell of the memory array, accumulate the weight with an increase based on the input, compare the accumulated weight to a threshold weight, and provide an output in response to the accumulated weight being greater than the threshold weight.

公开(公告)号：WO2015126518A2

公开(公告)日：2015-08-27

申请号：PCT/US2014/071597

申请日：2014-12-19

Applicant: RAMBUS INC.

Inventor： WARE, Frederick A. ,  TRINGALI, J. James ,  TSERN, Ely

IPC: G11C11/4063

CPC classification number: G06F11/1471 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0647 ,  G06F3/0685 ,  G06F2201/805 ,  G06F2201/84 ,  G11C7/20 ,  G11C14/0018

Abstract: The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.

Abstract translation: 本文描述的实施例描述了在包括用于易失性存储器和非易失性存储器的两个或更多存储器技术的多层存储器系统中的非易失性存储器持久性的技术。

公开(公告)号：WO2015094503A1

公开(公告)日：2015-06-25

申请号：PCT/US2014/064215

申请日：2014-11-06

Applicant: INTEL CORPORATION

Inventor： SCHAEFER, Andre ,  YEH, Jen-Chieh ,  LUO, Pei-Wen

IPC: G11C11/4063 ,  G11C11/409

CPC classification number: G11C7/1072 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/106 ,  G11C7/1066 ,  G11C8/10 ,  G11C8/12 ,  G11C11/4063 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/005 ,  G11C2207/107 ,  G11C2207/2209 ,  G11C2207/2272 ,  G11C2207/2281

Abstract: Examples are disclosed for accessing a dynamic random access memory (DRAM) array. In some examples, sub-arrays of a DRAM bank may be capable of opening multiple pages responsive to a same column address strobe. In other examples, sub-arrays of a DRAM bank may be arranged such that input/output (IO) bits may be routed in a serialized manner over an IO wire. For these other examples, the IO wire may pass through a DRAM die including the DRAM bank and/or may couple to a memory channel or bus outside of the DRAM die. Other examples are described and claimed.

Abstract translation: 公开了用于访问动态随机存取存储器（DRAM）阵列的示例。 在一些示例中，DRAM存储体的子阵列可以响应于相同的列地址选通而打开多个页面。 在其他示例中，DRAM组的子阵列可以被布置为使得输入/输出（IO）位可以通过IO线以串行方式路由。 对于这些其他示例，IO线可以通过包括DRAM组的DRAM裸片和/或可以耦合到DRAM裸片外部的存储器通道或总线。 其他的例子被描述和要求保护。

公开(公告)号：WO2014120215A1

公开(公告)日：2014-08-07

申请号：PCT/US2013/024179

申请日：2013-01-31

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： LI, Sheng ,  JOUPPI, Norman Paul

IPC: G11C7/00 ,  G11C11/4063

CPC classification number: G11C7/1072 ,  G06F12/0875 ,  G06F12/0893 ,  G06F2212/3042 ,  G06F2212/452 ,  G11C7/1084 ,  G11C11/4087 ,  G11C11/4093 ,  G11C15/00 ,  Y02D10/13

Abstract: According to an example, a method for adaptive-granularity row buffer (AG-RB) caching may include determining whether to cache data to a RB cache, and adjusting, by a processor or a memory side logic, an amount of the data to cache to the RB cache for different memory accesses, such as dynamic random-access memory (DRAM) accesses. According to another example, an AG-RB cache apparatus may include a 3D stacked DRAM including a plurality of DRAM dies including one or more DRAM banks, and a logic die including a RB cache. The AG-RB cache apparatus may further include a processor die including a memory controller including a predictor module to determine whether to cache data to the RB cache, and to adjust an amount of the data to cache to the RB cache for different DRAM accesses.

Abstract translation: 根据示例，用于自适应粒度行缓冲器（AG-RB）高速缓存的方法可以包括确定是否将数据高速缓存到RB缓存，并且由处理器或存储器侧逻辑调整要高速缓存的数据量 到用于不同存储器访问的RB缓存，例如动态随机存取存储器（DRAM）访问。 根据另一示例，AG-RB高速缓存装置可以包括包括包括一个或多个DRAM组的多个DRAM裸片的3D堆叠DRAM以及包括RB高速缓存的逻辑裸片。 AG-RB高速缓存装置还可以包括处理器管芯，该处理器管芯包括存储器控制器，该存储器控制器包括预测器模块，用于确定是否将数据高速缓存到所述RB高速缓存，并且为了不同的DRAM访问将所述数据量缓存到所述RB高速缓存。

公开(公告)号：WO2014106966A1

公开(公告)日：2014-07-10

申请号：PCT/KR2013/000558

申请日：2013-01-24

Applicant: 고려대학교 산학협력단

Inventor： 김선욱 ,  이호균 ,  최규현

IPC: G11C11/406 ,  G11C11/4063 ,  G11C11/401

CPC classification number: G11C11/40611 ,  G11C11/40622

Abstract: 본 발명은 동적 메모리 반도체 장치에서 선택적인 리프레쉬 방식을 통해 리프레쉬를 최소화하도록 한 읽기 및 쓰기 접근에 따른 선택적 리프레쉬 기능을 구비한 동적 메모리 장치 및 그 선택적 리프레쉬 방법에 관한 것이다.

Abstract translation: 本发明涉及一种具有基于读和写访问的选择性刷新功能的动态存储器件及其选择刷新方法，其中通过动态存储器半导体器件中的选择刷新方法使刷新操作最小化。

公开(公告)号：WO2014085268A1

公开(公告)日：2014-06-05

申请号：PCT/US2013/071534

申请日：2013-11-22

Applicant: INTEL CORPORATION ,  BAINS, Kuljit S.

Inventor： BAINS, Kuljit S.

IPC: G11C11/4063 ,  G11C11/406

CPC classification number: G11C11/4074 ,  G06F3/0604 ,  G06F3/0637 ,  G06F3/0673 ,  G06F13/1663 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1084 ,  G11C7/109 ,  G11C8/06 ,  G11C11/408 ,  Y10T29/41

Abstract: Techniques and mechanisms for determining a timing of a command to access a memory device resource. In an embodiment, a multi-cycle command which is exchanged from a memory controller to a memory device, wherein the multi-cycle command indicates an access to a bank of the memory device. Timing of the one or more other commands is controlled, based on the multi-cycle command, to enforce a time delay parameter which describes an operational constraint of the memory device. In another embodiment, timing of one or more commands is determined with reference to a beginning of a last cycle of a multi-cycle command.

Abstract translation: 用于确定访问存储器设备资源的命令的定时的技术和机制。 在一个实施例中，从存储器控制器交换到存储器件的多循环命令，其中多周期命令指示对存储器件的存储体的访问。 基于多周期命令来控制一个或多个其他命令的定时，以强制描述存储器件的操作约束的时间延迟参数。 在另一个实施例中，参考多循环命令的最后一个循环的开始来确定一个或多个命令的定时。

公开(公告)号：WO2014065775A1

公开(公告)日：2014-05-01

申请号：PCT/US2012/061257

申请日：2012-10-22

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： GAITHER, Blaine D. ,  EMMOT, Darel N. ,  WARNES, Lidia

IPC: G11C11/401 ,  G11C11/406 ,  G11C11/4063

CPC classification number: G11C11/40618 ,  G11C7/1072 ,  G11C11/40611 ,  G11C2211/4065

Abstract: An access of data in a memory device is sampled. In response to the sampled access of data, a refresh operation is performed in the memory device.

Abstract translation: 对存储器件中的数据进行采样。 响应于数据的采样访问，在存储器件中执行刷新操作。

公开(公告)号：WO2014065774A1

公开(公告)日：2014-05-01

申请号：PCT/US2012/061256

申请日：2012-10-22

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： EMMOT, Darel N.

IPC: G11C11/406 ,  G11C11/4063

CPC classification number: G11C11/4091 ,  G11C7/1072 ,  G11C11/40618 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50016

Abstract: A detection circuit is provided for a particular group of memory cells in a memory device, where the detection circuit is to be updated in response to at least one access of data and at least one neighboring group of memory cells. The particular group of memory cells is refreshed in response to an indication from the detection circuit, where the indication indicates presence of potential disturbance of the particular group of memory cells.

Abstract translation: 为存储器件中的特定存储器单元组提供检测电路，其中响应于数据的至少一个访问和至少一个相邻的存储器单元组来更新检测电路。 响应于来自检测电路的指示刷新特定组的存储器单元，其中指示表示特定存储器单元组的潜在干扰的存在。

公开(公告)号：WO2013037048A1

公开(公告)日：2013-03-21

申请号：PCT/CA2012/000849

申请日：2012-09-17

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： PYEON, Hong Beom

IPC: G11C29/00 ,  G11C11/4063 ,  G11C17/16

CPC classification number: G11C29/785 ,  G11C29/44 ,  G11C2029/1206 ,  G11C2029/4402

Abstract: Systems and methods are disclosed that may include a first layer comprising a first redundant memory element, an input/output interface, a first layer fuse box, and a fuse blowing control. These systems and methods also may include a second layer coupled to the first layer through a first connection comprising a second layer memory element and a second layer fuse box coupled to the first redundant memory element. In addition, these systems and methods may further include a redundancy register coupled to the first layer, wherein upon the failure of part of the second layer memory element, the redundancy register provides information to the fuse blowing control that allocates part of the first redundant memory element to provide redundancy for the failed part of the second layer memory element by blowing elements in the first layer fuse box and the second layer fuse box.

Abstract translation: 公开了可以包括包括第一冗余存储元件，输入/输出接口，第一层保险丝盒和保险丝熔断控制的第一层的系统和方法。 这些系统和方法还可以包括通过包括耦合到第一冗余存储器元件的第二层存储器元件和第二层熔丝盒的第一连接耦合到第一层的第二层。 另外，这些系统和方法还可以包括耦合到第一层的冗余寄存器，其中当第二层存储器元件的一部分出现故障时，冗余寄存器向熔丝吹制控制提供信息，该信号分配第一冗余存储器的一部分 元件，以通过在第一层熔丝盒和第二层熔丝盒中吹送元件来为第二层存储元件的故障部分提供冗余。