Invention Application
- Patent Title: METHODS FOR MANUFACTURING AN INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES
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Application No.: PCT/US2019/038590Application Date: 2019-06-21
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Publication No.: WO2020018236A1Publication Date: 2020-01-23
- Inventor: JIANG, Hao , REN, He , CHEN, Hao , NAIK, Mehul B.
- Applicant: APPLIED MATERIALS, INC.
- Applicant Address: 3050 Bowers Avenue Santa Clara, California 95054 US
- Assignee: APPLIED MATERIALS, INC.
- Current Assignee: APPLIED MATERIALS, INC.
- Current Assignee Address: 3050 Bowers Avenue Santa Clara, California 95054 US
- Agency: PATTERSON, B. Todd et al.
- Priority: US16/037,985 20180717
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/033 ; H01L21/311 ; H01L21/02
Abstract:
Generally, embodiments described herein relate to methods for manufacturing an interconnect structure for semiconductor devices, such as in a dual subtractive etch process. An embodiment is a method for semiconductor processing. A titanium nitride layer is formed over a substrate. A hardmask layer is formed over the titanium nitride layer. The hardmask layer is patterned into a pattern. The pattern is transferred to the titanium nitride layer, where the transferring comprises etching the titanium nitride layer. After transferring the pattern to the titanium nitride layer, the hardmask layer is removed, where the removal comprises performing an oxygen-containing ash process.
Information query
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