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    METHODS FOR MANUFACTURING AN INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES
    1.
    发明申请
    METHODS FOR MANUFACTURING AN INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：WO2020018236A1

    公开(公告)日：2020-01-23

    申请号：PCT/US2019/038590

    申请日：2019-06-21

    Applicant: APPLIED MATERIALS, INC.

    Inventor： JIANG, Hao ,  REN, He ,  CHEN, Hao ,  NAIK, Mehul B.

    IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L21/02

    Abstract: Generally, embodiments described herein relate to methods for manufacturing an interconnect structure for semiconductor devices, such as in a dual subtractive etch process. An embodiment is a method for semiconductor processing. A titanium nitride layer is formed over a substrate. A hardmask layer is formed over the titanium nitride layer. The hardmask layer is patterned into a pattern. The pattern is transferred to the titanium nitride layer, where the transferring comprises etching the titanium nitride layer. After transferring the pattern to the titanium nitride layer, the hardmask layer is removed, where the removal comprises performing an oxygen-containing ash process.

    METHOD TO REDUCE TRAP-INDUCED CAPACITANCE IN INTERCONNECT DIELECTRIC BARRIER STACK
    2.
    发明申请
    METHOD TO REDUCE TRAP-INDUCED CAPACITANCE IN INTERCONNECT DIELECTRIC BARRIER STACK 审中-公开
    减少互连电介质堆叠中的陷波电容的方法

    公开(公告)号：WO2017004075A1

    公开(公告)日：2017-01-05

    申请号：PCT/US2016/039881

    申请日：2016-06-28

    Applicant: APPLIED MATERIALS, INC.

    Inventor： REN, He ,  NAIK, Mehul B. ,  CAO, Yong ,  CHENG, Yana ,  YE, Weifeng

    IPC: H01L21/768 ,  H01L21/02

    CPC classification number: H01L21/02167 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/76826 ,  H01L21/76832

    Abstract: The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.

    Abstract translation: 本公开提供了形成在衬底上的互连和用于在衬底上形成互连的方法。 在一个实施例中，用于在衬底上形成互连的方法包括在衬底上沉积阻挡层，在阻挡层上沉积过渡层，以及在过渡层上沉积蚀刻停止层，其中过渡层共享共同 元件，并且其中所述过渡层与所述蚀刻停止层共享公共元件。

    METHODS FOR FORMING INTERCONNECTION STRUCTURES IN AN INTEGRATED CLUSTER SYSTEM FOR SEMICONDCUTOR APPLICATIONS
    6.
    发明申请
    METHODS FOR FORMING INTERCONNECTION STRUCTURES IN AN INTEGRATED CLUSTER SYSTEM FOR SEMICONDCUTOR APPLICATIONS 审中-公开
    用于形成用于半导体应用的集成集群系统中的互连结构的方法

    公开(公告)号：WO2015138056A1

    公开(公告)日：2015-09-17

    申请号：PCT/US2015/014096

    申请日：2015-02-02

    Applicant: APPLIED MATERIALS, INC.

    Inventor： NAIK, Mehul B. ,  NEMANI, Srinivas D. ,  KOSHIZAWA, Takehito ,  REN, He

    IPC: H01L21/768

    CPC classification number: H01L21/32136 ,  H01J37/321 ,  H01J37/32357 ,  H01J37/3244 ,  H01L21/02071 ,  H01L21/02274 ,  H01L21/32139 ,  H01L21/67184 ,  H01L21/67207 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76885

    Abstract: Embodiments of the present invention provide methods for forming an interconnection structure in semiconductor devices without breaking vacuum with minimum oxidation/atmosphere exposure. In one embodiment, a method for forming an interconnection structure for semiconductor devices includes supplying a barrier layer etching gas mixture into a first processing chamber having a substrate disposed therein to etch portions of a barrier layer exposed by a patterned metal layer until the underlying substrate is exposed, the first processing chamber disposed in a processing system, and forming a liner layer on the substrate covering the etched barrier layer in a second processing chamber disposed in the processing system.

    Abstract translation: 本发明的实施例提供了在半导体器件中形成互连结构而不破坏最小氧化/大气暴露的真空的方法。 在一个实施例中，用于形成用于半导体器件的互连结构的方法包括将阻挡层蚀刻气体混合物供应到具有设置在其中的衬底的第一处理室中，以蚀刻由图案化金属层暴露的阻挡层的部分，直到下面的衬底为 暴露的第一处理室，设置在处理系统中，并且在布置在处理系统中的第二处理室中，在覆盖蚀刻的阻挡层的基板上形成衬垫层。

    DOPED SELECTIVE METAL CAPS TO IMPROVE COPPER ELECTROMIGRATION WITH RUTHENIUM LINER
    7.
    发明申请
    DOPED SELECTIVE METAL CAPS TO IMPROVE COPPER ELECTROMIGRATION WITH RUTHENIUM LINER 审中-公开
    多孔选择性金属盖，以改善铜电钌与钌衬里

    公开(公告)号：WO2018063815A1

    公开(公告)日：2018-04-05

    申请号：PCT/US2017/051566

    申请日：2017-09-14

    Applicant: APPLIED MATERIALS, INC.

    Inventor： NAIK, Mehul B. ,  WU, Zhiyuan

    IPC: H01L21/768

    Abstract: Embodiments of the present disclosure are related to improved methods for forming a structure in a substrate. In one implementation, the method includes forming a recess in the substrate, forming a barrier layer on exposed surfaces of the substrate and exposed surfaces of the recess, forming an intermediate layer on the barrier layer, forming a metal fill layer on the intermediate layer and overfill the recess, planarizing the metal fill layer to expose the barrier layer, the intermediate layer, and a top surface of the substrate, selectively forming a cobalt layer on the metal fill layer, and exposing the substrate to an aluminum-containing precursor to selectively form a cobalt-aluminum alloy layer on at least a top surface of the cobalt layer.

    Abstract translation: 本公开的实施例涉及用于在衬底中形成结构的改进方法。 在一个实施方式中，该方法包括在衬底中形成凹槽，在衬底的暴露表面上和凹槽的暴露表面上形成阻挡层，在阻挡层上形成中间层，在中间层上形成金属填充层以及 过度填充凹陷，平坦化金属填充层以暴露阻挡层，中间层和衬底的顶表面，在金属填充层上选择性地形成钴层，并将衬底暴露于含铝前体以选择性地 在钴层的至少顶面上形成钴 - 铝合金层。

    DIRECT DEPOSITION OF NICKEL SILICIDE NANOWIRE
    8.
    发明申请
    DIRECT DEPOSITION OF NICKEL SILICIDE NANOWIRE 审中-公开
    直接沉积镍硅纳米管

    公开(公告)号：WO2016111833A1

    公开(公告)日：2016-07-14

    申请号：PCT/US2015/066870

    申请日：2015-12-18

    Applicant: APPLIED MATERIALS, INC.

    Inventor： LAKSHMANAN, Annamalai ,  MEBARKI, Bencherki ,  SINGH, Kaushal K. ,  MA, Paul F. ,  NAIK, Mehul B. ,  COCKBURN, Andrew ,  GODET, Ludovic

    IPC: H01L21/441 ,  H01L21/203

    CPC classification number: H01L21/76879 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76876 ,  H01L21/76886 ,  H01L21/76889 ,  H01L23/53257 ,  H01L23/53271 ,  H01L2221/1094

    Abstract: Methods for direct deposition of a metal silicide nanowire for back-end interconnection structures for semiconductor applications are provided. In one embodiment, the method includes positioning a substrate in a processing region of a process chamber, the substrate having a first surface comprising a non-dielectric material; and a dielectric layer formed on the first surface. An opening is formed in the dielectric layer, the opening exposing at least a portion of the first surface, the opening having sidewalls. A metal silicide seed is deposited in the opening using a PVD process, wherein the PVD process is performed with either no bias or a bias which creates deposition on the sidewall which is less than 1% of the deposition on the first surface. A metal silicide layer is then selectively deposited on the metal silicide seed using a metal-silicon organic precursor, creating the metal silicide nanowire.

    Abstract translation: 提供了用于半导体应用的后端互连结构的金属硅化物纳米线的直接沉积的方法。 在一个实施例中，该方法包括将衬底定位在处理室的处理区域中，该衬底具有包含非电介质材料的第一表面; 以及形成在第一表面上的电介质层。 在电介质层中形成开口，该开口露出第一表面的至少一部分，该开口具有侧壁。 使用PVD工艺在开口中沉积金属硅化物种子，其中PVD工艺是在无偏压或偏压的情况下进行的，其产生在侧壁上的沉积，其小于第一表面上的沉积的1％。 然后使用金属硅有机前体将金属硅化物层选择性地沉积在金属硅化物种子上，产生金属硅化物纳米线。

    METHODS FOR FORMING A METAL SILICIDE INTERCONNECTION NANOWIRE STRUCTURE
    9.
    发明申请
    METHODS FOR FORMING A METAL SILICIDE INTERCONNECTION NANOWIRE STRUCTURE 审中-公开
    形成金属硅化物互连纳米结构的方法

    公开(公告)号：WO2016069132A1

    公开(公告)日：2016-05-06

    申请号：PCT/US2015/050845

    申请日：2015-09-18

    Applicant: APPLIED MATERIALS, INC.

    Inventor： MEBARKI, Bencherki ,  LAKSHMANAN, Annamalai ,  SINGH, Kaushal K. ,  COCKBURN, Andrew ,  GODET, Ludovic ,  MA, Paul F. ,  NAIK, Mehul B.

    IPC: H01L21/28

    CPC classification number: H01J37/32192 ,  C23C16/42 ,  C23C16/56 ,  H01J37/32091 ,  H01J37/32321 ,  H01J37/32339 ,  H01L21/2686 ,  H01L21/28556 ,  H01L21/32053 ,  H01L21/76885

    Abstract: Methods and apparatus for forming a metal silicide as nanowires for back-end interconnection structures for semiconductor applications are provided. In one embodiment, the method includes forming a metal silicide layer on a substrate by a chemical vapor deposition process or a physical vapor deposition process, thermal treating the metal silicide layer in a processing chamber, applying a microwave power in the processing chamber while thermal treating the metal silicide layer; and maintaining a substrate temperature less than 400 degrees Celsius while thermal treating the metal silicide layer. In another embodiment, a method includes supplying a deposition gas mixture including at least a metal containing precursor and a reacting gas on a surface of a substrate, forming a plasma in the presence of the deposition gas mixture by exposure to microwave power, exposing the plasma to light radiation, and forming a metal silicide layer on the substrate from the deposition gas.

    Abstract translation: 提供了用于形成用于半导体应用的后端互连结构的纳米线的金属硅化物的方法和装置。 在一个实施例中，该方法包括通过化学气相沉积工艺或物理气相沉积工艺在衬底上形成金属硅化物层，对处理室中的金属硅化物层进行热处理，在处理室中施加微波功率，同时热处理 金属硅化物层; 并且在热处理金属硅化物层的同时保持低于400摄氏度的衬底温度。 在另一个实施方案中，一种方法包括在衬底的表面上提供至少包含含金属的前体和反应气体的沉积气体混合物，通过暴露于微波功率在沉积气体混合物的存在下形成等离子体，使等离子体 以照射辐射，并从沉积气体在衬底上形成金属硅化物层。

    INTEGRATED METAL SPACER AND AIR GAP INTERCONNECT
    10.
    发明申请
    INTEGRATED METAL SPACER AND AIR GAP INTERCONNECT 审中-公开
    集成金属间隔和空气间隙互连

    公开(公告)号：WO2015153040A1

    公开(公告)日：2015-10-08

    申请号：PCT/US2015/018528

    申请日：2015-03-03

    Applicant: APPLIED MATERIALS, INC.

    Inventor： REN, He ,  NAIK, Mehul B.

    IPC: H01L21/764

    CPC classification number: H01L21/76802 ,  H01L21/02126 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/32136 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76889

    Abstract: Embodiments described herein relate to methods for forming an air gap interconnect. A metal spacer layer is conformally deposited on a substrate having mandrel structures formed thereon. The metal spacer layer is etched to form spacer features and the mandrel structures are removed from the substrate. Various other dielectric deposition, patterning and etching steps may be performed to desirably pattern materials present on the substrate. Ultimately, a trench is formed between adjacent spacer features and a capping layer is deposited over the trench to form an air gap between the adjacent spacer features. For packaging purposes, an interconnect via may be configured to contact at least one of the spacer features adjacent the air gap.

    Abstract translation: 本文所述的实施例涉及形成气隙互连的方法。 金属间隔层共形沉积在其上形成有心轴结构的基底上。 蚀刻金属间隔层以形成间隔物特征，并且将芯棒结构从基底上移除。 可以进行各种其它介电沉积，图案化和蚀刻步骤以期望地存在于基板上的材料。 最终，在相邻间隔物特征之间形成沟槽，并且在沟槽上沉积覆盖层以在相邻间隔物特征之间形成气隙。 为了包装目的，互连通孔可以被配置为接触邻近气隙的间隔件特征中的至少一个。

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