A memory device (10) may include a phase driver circuit (36) that may output a first voltage for refreshing a plurality of memory cells. The memory device (10) may also include a plurality of word line driver circuits (42) that may receive the first voltage via the phase driver circuit (36), such that each word line driver circuit (42) of the plurality of word line driver circuits (42) may provide the first voltage to a respective word line (WL) associated with a respective portion of the plurality of memory cells. In addition, each word line driver circuit (42) may refresh the respective portion of the plurality of memory cells based on a respective word line enable signal provided to a first switch of the respective word line driver circuit (42).