公开(公告)号：WO2021211532A1

公开(公告)日：2021-10-21

申请号：PCT/US2021/027013

申请日：2021-04-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： BELL, Debra M. ,  REHMEYER, James S. ,  DODDS, Brett K. ,  VECHES, Anthony D. ,  WANG, Libo ,  WU, Di

IPC: G06F9/455 ,  G06F9/50 ,  G06F11/30 ,  H04L29/08

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods for an internet of things (loT) system to include edge devices that perform at least some functions without communicating with a cloud computing system. An edge device may include a memory with on-memory pattern matching capabilities. The edge device may perform pattern matching operations on data collected by the edge device or sensors in communication with the edge device. Based on results of the pattern matching operations, the edge device may perform various functions, such as transmitting data to the cloud computing system, activating an alarm, and/or changing a frequency at which data is transmitted.

公开(公告)号：WO2021178179A1

公开(公告)日：2021-09-10

申请号：PCT/US2021/019435

申请日：2021-02-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： BELL, Debra M. ,  WANG, Libo ,  WU, Di ,  REHMEYER, James S. ,  VECHES, Anthony D.

IPC: G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods, and memories that are capable of performing pattern matching operations within a memory device. The pattern matching operations may be performed on data stored within the memory based on a pattern stored in a register. The result of the pattern matching operation may be provided by the memory. The data on which the pattern matching operation is performed may not be output from the memory during the pattern matching operation.

公开(公告)号：WO2019112937A1

公开(公告)日：2019-06-13

申请号：PCT/US2018/063570

申请日：2018-12-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： REHMEYER, James S. ,  COWLES, Timothy B.

IPC: G06F3/06 ,  G11C7/06

Abstract: The present disclosure includes apparatuses and methods related to data movement operations in non-volatile memory. An example apparatus can comprise an array of non-volatile memory cells including a plurality of sections each with a plurality of rows and a controller configured to move data stored in a first portion of the array from a first row of a first section to a second row of the first section and move data stored in a second portion of the array from a second section to the first to create an open row in the second section in response to data from a particular number of portions of memory cells in the first section being moved within the first section.

公开(公告)号：WO2022010765A1

公开(公告)日：2022-01-13

申请号：PCT/US2021/040246

申请日：2021-07-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： REHMEYER, James S. ,  JOHNSON, Jason M. ,  LEE, Joo-Sang

IPC: G11C11/406 ,  G11C7/04 ,  G11C11/408 ,  G11C5/04 ,  G06F3/06

Abstract: Memory devices, systems, and associated methods with per die temperature-compensated refresh control, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory cells and a sensor configured to measure a temperature of the memory device. The memory device determines a frequency at which it is receiving refresh commands. The memory device is further configured to skip refresh operations of the memory cells based, at least in part, on the determination and on the temperature of the memory device.

公开(公告)号：WO2021206903A1

公开(公告)日：2021-10-14

申请号：PCT/US2021/023700

申请日：2021-03-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： WU, Di ,  BELL, Debra M. ,  VECHES, Anthony D. ,  REHMEYER, James S. ,  WANG, Libo

IPC: G11C11/4093 ,  G11C11/4076 ,  G11C11/408 ,  G06F3/06 ,  G11C7/10

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for command/address tracking in memory. Tracking circuitry may be used to determine if commands and/or command sequences include illegal commands and/or illegal command sequences. If the commands and/or command sequences include illegal commands and/or illegal command sequences, the tracking circuitry may activate signals that prevent execution of the commands and/or notice of the detected illegal commands and/or command sequences.

公开(公告)号：WO2021206892A1

公开(公告)日：2021-10-14

申请号：PCT/US2021/023250

申请日：2021-03-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： WU, Di ,  VECHES, Anthony D. ,  REHMEYER, James S. ,  BELL, Debra M. ,  WANG, Libo

IPC: G11C11/4093 ,  G06N3/08 ,  G06F3/06 ,  G11C11/4076 ,  G11C7/10

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods for performing operations associated with machine learning. Machine learning operations may include processing a data set, training a machine learning algorithm, and applying a trained algorithm to a data set. Some of the machine learning operations, such as pattern matching operations, may be performed within a memory device.

公开(公告)号：WO2021173338A1

公开(公告)日：2021-09-02

申请号：PCT/US2021/017228

申请日：2021-02-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： REHMEYER, James S. ,  WANG, Libo ,  VECHES, Anthony D. ,  BELL, Debra M. ,  WU, Di

IPC: G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G06F3/06

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods, and memories that are capable of performing pattern matching operations within a memory device. The pattern matching operations may be performed on data stored within the memory based on a pattern stored in a register, lire result of the pattern matching operation may be provided by the memory. The data may be retrieved from a memory array for the pattern matching operation by a read operation, a refresh operation, an error correction operation, and/or a pattern matching operation. The data may be retrieved from incoming data input lines instead of or in addition to the memory array. How the data is stored or retrieved for pattern matching operations may be controlled by a memory controller.

公开(公告)号：WO2020247639A1

公开(公告)日：2020-12-10

申请号：PCT/US2020/036133

申请日：2020-06-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： REHMEYER, James S. ,  MEIER, Nathaniel J. ,  LEE, Joo-Sang

IPC: G11C11/406 ,  G11C5/02 ,  G06F3/06

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for staggering the timing of skipped refresh operations on a memory. Memory cells of memories may need to periodically perform refresh operations. In some instances, auto-refresh operations may be periodically skipped when charge retention characteristics of the memory cells of the memory exceed the auto-refresh frequency. To reduce peak current draw during refresh operations, the skipped refresh operations may be staggered across different portions of the memory. In one example, the skipped refresh operation may be staggered in time among memory dies of the memory to limit a number of memory dies that are performing an auto-refresh operation to a maximum number. In another example, the skipped refresh operation may be staggered in time among memory banks of a single memory array to limit a number of memory banks that are performing an auto-refresh operation to a maximum number.

公开(公告)号：WO2020206333A1

公开(公告)日：2020-10-08

申请号：PCT/US2020/026689

申请日：2020-04-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MEIER, Nathaniel J. ,  REHMEYER, James S.

IPC: G11C11/406 ,  G11C11/408 ,  G11C8/06 ,  G11C8/12

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for staggering the timing of targeted refresh operations, A memory device may include a number of memory banks, at least some of which may be simultaneously entered into a refresh mode. A given memory bank may perform an auto-refresh operation or a targeted refresh operation, which may draw less power than the auto-refresh operation. The timing of the targeted refresh operations may be staggered between the refreshing memory banks, such that a portion of the refreshing memory banks are performing a targeted refresh operation simultaneously with a portion of the refreshing memory banks performing an auto-refresh operation.

公开(公告)号：WO2020149894A1

公开(公告)日：2020-07-23

申请号：PCT/US2019/053847

申请日：2019-09-30

Applicant: MICRON TECHNOLOGY, INC

Inventor： REHMEYER, James S. ,  BELL, Debra M. ,  RAAD, George B. ,  CALLAWAY, Brian P. ,  ALZHEIMER, Joshua E.

IPC: G11C11/408 ,  G11C11/406 ,  G11C11/4074

Abstract: A memory device (10) may include a phase driver circuit (36) that may output a first voltage for refreshing a plurality of memory cells. The memory device (10) may also include a plurality of word line driver circuits (42) that may receive the first voltage via the phase driver circuit (36), such that each word line driver circuit (42) of the plurality of word line driver circuits (42) may provide the first voltage to a respective word line (WL) associated with a respective portion of the plurality of memory cells. In addition, each word line driver circuit (42) may refresh the respective portion of the plurality of memory cells based on a respective word line enable signal provided to a first switch of the respective word line driver circuit (42).