Invention Application
- Patent Title: STACKABLE FULLY MOLDED SEMICONDUCTOR STRUCTURE WITH VERTICAL INTERCONNECTS
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Application No.: PCT/US2020/038440Application Date: 2020-06-18
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Publication No.: WO2020257458A2Publication Date: 2020-12-24
- Inventor: OLSON, Timothy, L. , HUDSON, Edward , BISHOP, Craig
- Applicant: DECA TECHNOLOGIES INC.
- Applicant Address: 7855 South River Parkway, Ste. 111 Tempe, AZ 85284 US
- Assignee: DECA TECHNOLOGIES INC.
- Current Assignee: DECA TECHNOLOGIES INC.
- Current Assignee Address: 7855 South River Parkway, Ste. 111 Tempe, AZ 85284 US
- Agency: BURNHAM, Bryce, W.
- Priority: US16/904,404 20200617; US62/863,179 20190618
Abstract:
A method of making a semiconductor device may include providing a carrier and forming a first photoresist over the carrier with first openings through the first photoresist. A non-planar conductive seed layer may be formed over the first photoresist and conformally extend into the first openings through the first photoresist. A second photoresist may be formed over the first photoresist and over the non-planar conductive seed layer. The second photoresist layer may be patterned to form second openings through the second photoresist that extend to the non-planar conductive seed layer. Conductive posts may be plated over the non-planar conductive seed layer and within the second openings. The second photoresist may be removed while leaving in place the first photoresist. A semiconductor die may be coupled to the carrier. The semiconductor die, the conductive posts, and the first photoresist may be encapsulated with mold compound.
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