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    THERMALLY ENHANCED FULLY MOLDED FAN-OUT MODULE
    1.
    发明申请
    THERMALLY ENHANCED FULLY MOLDED FAN-OUT MODULE 审中-公开
    热成型完全模制的风扇模块

    公开(公告)号：WO2017049269A1

    公开(公告)日：2017-03-23

    申请号：PCT/US2016/052436

    申请日：2016-09-19

    Applicant: DECA TECHNOLOGIES INC.

    Inventor： SCANLAN, Christopher, M.

    IPC: H01L21/78

    CPC classification number: H01L25/50 ,  H01L21/4853 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/552 ,  H01L24/09 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0655 ,  H01L2221/68354 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2924/3511

    Abstract: A method of making a semiconductor device can include providing a temporary carrier with adhesive. A first semiconductor die and a second semiconductor die can be mounted face up to the temporary carrier such that back surfaces of the first semiconductor die and the second semiconductor die are depressed within the adhesive. An embedded die panel can be formed by encapsulating at least four sides surfaces and an active surface of the first semiconductor die, the second semiconductor die, and side surfaces of the conductive interconnects in a single step. The conductive interconnects of the first semiconductor die and the second semiconductor die can be interconnected without a silicon interposer by forming a fine-pitch build-up interconnect structure over the embedded die panel to form at least one molded core unit. The at least one molded core unit can be mounted to an organic multi-layer substrate.

    Abstract translation: 制造半导体器件的方法可以包括提供具有粘合剂的临时载体。 可以将第一半导体管芯和第二半导体管芯面朝上安装到临时载体上，使得第一半导体管芯和第二半导体管芯的背面在粘合剂内被压下。 可以通过在一个步骤中封装至少四个侧表面和第一半导体管芯，第二半导体管芯和导电互连的侧表面的有源表面来形成嵌入式裸片。 第一半导体管芯和第二半导体管芯的导电互连可以通过在嵌入的模具面板上形成微细间距建立互连结构而形成至少一个模制的核心单元，而不需要通过硅插入器来互连。 所述至少一个成型芯单元可以安装到有机多层基板上。

    SEMICONDUCTOR DEVICE AND METHOD OF UNIT SPECIFIC PROGRESSIVE ALIGNMENT
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF UNIT SPECIFIC PROGRESSIVE ALIGNMENT 审中-公开
    半导体器件和单元特定逐步对准方法

    公开(公告)号：WO2018053441A1

    公开(公告)日：2018-03-22

    申请号：PCT/US2017/052095

    申请日：2017-09-18

    Applicant: DECA TECHNOLOGIES INC.

    Inventor： BISHOP, Craig ,  SCANLAN, Christopher, M.

    IPC: H01L21/66

    Abstract: A semiconductor device and method can comprise measuring a true position of each of a plurality of semiconductor die within an embedded die panel and determining a total radial shift of each of the plurality of semiconductor die. The total radial shift of each of the plurality of semiconductor die can be distributed to two or more layers for each of the plurality of semiconductor die by assigning a portion of the total radial shift to each of the layers according to a priority list to form a distributed radial shift for each of the layers. A transformation for each of the layers for each of the plurality of semiconductor die can be transformed using the distributed radial shift for each of the layers. A unit specific pattern can be formed over each of the plurality of semiconductor die with the transformation for each of the layers.

    Abstract translation: 半导体器件和方法可以包括测量多个半导体裸片中的每一个在嵌入式裸片面板内的真实位置并且确定多个半导体裸片中的每一个的总径向偏移。 通过根据优先级列表将全部径向偏移的一部分分配给每个层，可以将多个半导体管芯中的每一个的全部径向偏移分配到用于多个半导体管芯中的每一个的两个或更多个层以形成 为每个层分布径向偏移。 对于多个半导体管芯中的每个半导体管芯的每个层的变换可以使用用于每个层的分布式径向偏移来变换。 通过每层的转换可以在多个半导体管芯中的每一个上形成单元特定图案。

    TWO STEP METHOD OF RAPID CURING A SEMICONDUCTOR POLYMER LAYER
    5.
    发明申请
    TWO STEP METHOD OF RAPID CURING A SEMICONDUCTOR POLYMER LAYER 审中-公开
    快速固化半导体聚合物层的两步法

    公开(公告)号：WO2015042121A1

    公开(公告)日：2015-03-26

    申请号：PCT/US2014/056042

    申请日：2014-09-17

    Applicant: DECA TECHNOLOGIES INC.

    Inventor： ROGERS, William, Boyd ,  VAN DEN HOEK, Willibrordus Gerardus, Maria

    IPC: H01L21/312

    CPC classification number: H01L21/02118 ,  H01L21/31058 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76814 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05575 ,  H01L2224/056 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

    Abstract: A semiconductor device and method of making the semiconductor device is described. A semiconductor die is provided. A polymer layer is formed over the semiconductor die. A via is formed in the polymer layer. The polymer layer is crosslinked in a first process. The polymer layer is thermally cured in a second process. The polymer layer can comprise polybenzoxazoles (PBO), polyimide, benzocyclobutene (BCB), or siloxane-based polymers. A surface of the polymer layer can be crosslinked by a UV bake to control a slope of the via during subsequent curing. The second process can further comprise thermally curing the polymer layer using conduction, convection, infrared, or microwave heating. The polymer layer can be thermally cured by increasing a temperature of the polymer at a rate greater than or equal to 10 degrees Celsius per minute, and can be completely cured in less than or equal to 60 minutes.

    Abstract translation: 描述制造半导体器件的半导体器件和方法。 提供半导体管芯。 聚合物层形成在半导体管芯上。 在聚合物层中形成通孔。 聚合物层在第一工艺中交联。 聚合物层在第二工序中热固化。 聚合物层可以包含聚苯并恶唑（PBO），聚酰亚胺，苯并环丁烯（BCB）或硅氧烷基聚合物。 聚合物层的表面可以通过UV烘烤来交联，以在后续固化期间控制通孔的斜率。 第二种方法还可以包括使用传导，对流，红外或微波加热来热固化聚合物层。 聚合物层可以通过以大于或等于10摄氏度/分钟的速率增加聚合物的温度来热固化，并且可以在小于或等于60分钟内完全固化。

    STACKABLE FULLY MOLDED SEMICONDUCTOR STRUCTURE WITH VERTICAL INTERCONNECTS
    6.
    发明申请
    STACKABLE FULLY MOLDED SEMICONDUCTOR STRUCTURE WITH VERTICAL INTERCONNECTS 审中-公开

    公开(公告)号：WO2020257458A2

    公开(公告)日：2020-12-24

    申请号：PCT/US2020/038440

    申请日：2020-06-18

    Applicant: DECA TECHNOLOGIES INC.

    Inventor： OLSON, Timothy, L. ,  HUDSON, Edward ,  BISHOP, Craig

    Abstract: A method of making a semiconductor device may include providing a carrier and forming a first photoresist over the carrier with first openings through the first photoresist. A non-planar conductive seed layer may be formed over the first photoresist and conformally extend into the first openings through the first photoresist. A second photoresist may be formed over the first photoresist and over the non-planar conductive seed layer. The second photoresist layer may be patterned to form second openings through the second photoresist that extend to the non-planar conductive seed layer. Conductive posts may be plated over the non-planar conductive seed layer and within the second openings. The second photoresist may be removed while leaving in place the first photoresist. A semiconductor die may be coupled to the carrier. The semiconductor die, the conductive posts, and the first photoresist may be encapsulated with mold compound.

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