A 3D memory device (100) includes a substrate (102), a gate electrode (104) above the substrate (102), a blocking layer (106) on the gate electrode (104), a plurality of charge trapping layers (108a, 108b, 108c) on the blocking layer (106), a tunneling layer (110) on the plurality of charge trapping layers (108a, 108b, 108c), and a plurality of channel layers (112a, 112b, 112c) on the tunneling layer (110). The plurality of charge trapping layers (108a, 108b, 108c) are discrete and disposed at different levels. The plurality of channel layers (112a, 112b, 112c) are discrete and disposed at disposed at different levels. Each of the channel layers (112a, 112b, 112c) corresponds to a respective one of the charge trapping layers (108a, 108b, 108c).