The present disclosure provides a memory device. The memory device comprises: a first group of memory cells and a second group of memory cells, the memory cells of the second group being programmed to a predefined logic state of at least two logic states; and a memory controller coupled to the memory cells. The memory controller is configured to: apply a reading voltage to the memory cells of the second group to assess the logic state thereof; and if the logic state of at least one memory cell of the second group is assessed to be different from the predefined logic state, perform a refresh operation of the memory cells of the first group by applying thereto a recovery voltage higher than the reading voltage to assess the logic state thereof and then reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage.