公开(公告)号：WO2019156856A1

公开(公告)日：2019-08-15

申请号：PCT/US2019/015678

申请日：2019-01-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： TORTORELLI, Innocenzo ,  ROBUSTELLI, Mattia

IPC: H01L27/02 ,  H01L27/06 ,  H01L21/306

Abstract: Methods and devices based on the use of dopant-modulated etching are described. During fabrication, a memory storage element of a memory cell may be non-uniformly doped with a dopant that affects a subsequent etching rate of the memory storage element. After etching, the memory storage element may have an asymmetric geometry or taper profile corresponding to the non-uniform doping concentration. A multi-deck memory device may also be formed using dopant-modulated etching. Memory storage elements on different memory decks may have different taper profiles and different doping gradients.

公开(公告)号：WO2018080615A1

公开(公告)日：2018-05-03

申请号：PCT/US2017/046585

申请日：2017-08-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： PIROVANO, Agostino ,  TORTORELLI, Innocenzo ,  REDAELLI, Andrea ,  PELLIZZER, Fabio

IPC: G11C5/02 ,  G11C11/00

Abstract: Disclosed herein is a memory cell including a memory element and a selector device. The memory cell may be programmed with a programming pulse having a first polarity and read with a read pulse having a second polarity. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities. The memory cell may exhibit reduced voltage drift and/or threshold voltage distribution. Described herein is a memory cell that acts as both a memory element and a selector device. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities.

Abstract translation: 这里公开了一种包括存储器元件和选择器装置的存储器单元。 存储器单元可以用具有第一极性的编程脉冲编程并且用具有第二极性的读取脉冲读取。 存储器单元可以用具有第一和第二部分的编程脉冲编程。 第一和第二部分可以具有不同的大小和极性。 存储器单元可以表现出降低的电压漂移和/或阈值电压分布。 这里描述的是充当存储器元件和选择器器件的存储器单元。 存储器单元可以用具有第一和第二部分的编程脉冲编程。 第一和第二部分可以具有不同的大小和极性。

公开(公告)号：WO2017078988A1

公开(公告)日：2017-05-11

申请号：PCT/US2016/058714

申请日：2016-10-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： TORTORELLI, Innocenzo ,  TANG, Stephen ,  PAPAGIANNI, Christina

IPC: G11C7/10 ,  G11C7/06

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/005 ,  G11C2013/0052 ,  G11C2013/0073 ,  G11C2213/76 ,  G11C2213/77

Abstract: Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying write pulses having different polarities. Different polarities of the write pulses may program different logic states into the memory cell. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities of the write pulses.

Abstract translation: 这里公开了一种存储单元。 存储器单元可以充当组合选择器装置和存储器元件。 存储器单元可以通过施加具有不同极性的写入脉冲来编程。 写入脉冲的不同极性可以将不同的逻辑状态编程到存储器单元中。 存储单元可以通过全部具有相同极性的读取脉冲来读取。 存储器单元的逻辑状态可以通过在施加读取脉冲时观察不同的阈值电压来检测。 不同的阈值电压可以响应写入脉冲的不同极性。

公开(公告)号：WO2021002995A1

公开(公告)日：2021-01-07

申请号：PCT/US2020/035816

申请日：2020-06-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： TORTORELLI, Innocenzo

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08 ,  G11C11/54 ,  G11C13/00

Abstract: In an example, an apparatus can include an array of variable resistance memory cells and a neural memory controller coupled to the array of variable resistance memory cells and configured to apply a sub-threshold voltage pulse to a variable resistance memory cell of the array to change a threshold voltage of the variable resistance memory cell in an analog fashion from a voltage associated with a reset state to effectuate a first synaptic weight change; and apply additional sub-threshold voltage pulses to the variable resistance memory cell to effectuate each subsequent synaptic weight change.

公开(公告)号：WO2019023049A1

公开(公告)日：2019-01-31

申请号：PCT/US2018/043012

申请日：2018-07-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： SFORZIN, Marco ,  AMATO, Paolo ,  TORTORELLI, Innocenzo ,  DALLABORA, Marco

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34

Abstract: The present disclosure includes apparatuses and methods related to program operations in memory. An example apparatus can perform a program operation on an array of memory cells by applying a first program signal to a first portion of the array of memory cells that are to remain in a first state in response to the program operation, wherein the first program signal programs memory cells to a second state and then to the first state.

公开(公告)号：WO2018186997A1

公开(公告)日：2018-10-11

申请号：PCT/US2018/021948

申请日：2018-03-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： PELLIZZER, Fabio ,  TORTORELLI, Innocenzo ,  PIROVANO, Agostino ,  REDAELLI, Andrea

IPC: H01L45/00

Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.

公开(公告)号：WO2018031217A1

公开(公告)日：2018-02-15

申请号：PCT/US2017/043245

申请日：2017-07-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： TORTORELLI, Innocenzo ,  MEYER, Russell L. ,  PIROVANO, Agostino ,  REDAELLI, Andrea ,  FRATIN, Lorenzo ,  PELLIZZER, Fabio

IPC: G11C11/56

Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.

Abstract translation: 这里公开了一种包括存储器元件和选择器装置的存储器单元。 数据可以存储在存储器元件和选择器装置中。 存储单元可以通过施加具有不同极性和大小的写入脉冲来编程。 写入脉冲的不同极性可以将不同的逻辑状态编程到选择器装置中。 写脉冲的不同大小可以将不同的逻辑状态编程到存储器元件中。 存储单元可以通过全部具有相同极性的读取脉冲来读取。 存储器单元的逻辑状态可以通过在施加读取脉冲时观察不同的阈值电压来检测。 不同的阈值电压可以响应写入脉冲的不同极性和大小。

公开(公告)号：WO2015130455A1

公开(公告)日：2015-09-03

申请号：PCT/US2015/015023

申请日：2015-02-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： RAVASIO, Marcello ,  SCIARRILLO, Samuele ,  PELLIZZER, Fabio ,  TORTORELLI, Innocenzo ,  SOMASCHINI, Roberto ,  CASELLATO, Cristina ,  MOTTADELLI, Riccardo

IPC: H01L45/00 ,  H01L43/02 ,  H01L49/00 ,  H01L27/115

CPC classification number: H01L27/2463 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same, in one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.

Abstract translation: 所公开的技术通常涉及集成电路器件，特别是涉及交叉点存储器阵列及其制造方法，一方面，制造交叉点存储器阵列的方法包括形成存储单元材料堆叠，其包括第一 活性材料和第一活性材料上的第二活性材料，其中所述第一和第二活性材料中的一种包含储存材料，所述第一和第二活性材料中的另一种包括选择材料。 制造交叉点阵列的方法还包括对存储单元材料堆叠进行图案化，其包括通过存储单元材料堆叠的第一和第二活性材料中的至少一个的蚀刻，在至少一个的至少一个的侧壁上形成保护衬垫 在蚀刻通过第一和第二活性材料之一之后蚀刻第一和第二活性材料，并且在第一和第二活性材料之一的侧壁上形成保护衬垫之后进一步蚀刻存储单元材料堆叠。

公开(公告)号：WO2021167796A1

公开(公告)日：2021-08-26

申请号：PCT/US2021/016630

申请日：2021-02-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： TORTORELLI, Innocenzo ,  GIDUTURI, Hari ,  PELLIZZER, Fabio

IPC: G11C13/00 ,  G06F3/06

Abstract: Methods, systems, and devices for varying-polarity read operations for polarity-written memory cells are described. Memory cells may be programmed to store different logic values based on applying write voltages of different polarities to the memory cells. A memory device may read the logic values based on applying read voltages to the memory cells, and the polarity of the read voltages may vary such that at least some read voltages have one polarity and at least some read voltages have another polarity. The read voltage polarity may vary randomly or according to a pattern and may be controlled by the memory device or by a host device for the memory device.

公开(公告)号：WO2021111159A1

公开(公告)日：2021-06-10

申请号：PCT/IB2019/001205

申请日：2019-12-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： TORTORELLI, Innocenzo ,  AMATO, Paolo ,  SFORZIN, Marco

IPC: G11C13/00 ,  G06F3/06 ,  G11C29/02

Abstract: The present disclosure provides a memory device. The memory device comprises: a first group of memory cells and a second group of memory cells, the memory cells of the second group being programmed to a predefined logic state of at least two logic states; and a memory controller coupled to the memory cells. The memory controller is configured to: apply a reading voltage to the memory cells of the second group to assess the logic state thereof; and if the logic state of at least one memory cell of the second group is assessed to be different from the predefined logic state, perform a refresh operation of the memory cells of the first group by applying thereto a recovery voltage higher than the reading voltage to assess the logic state thereof and then reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage.