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发明申请
WO2021142599A1 一种芯片封装结构及封装方法 审中-公开

一种芯片封装结构及封装方法
摘要：
本申请实施例提供一种芯片封装结构及封装方法，其中，芯片封装结构包括：基板，基板上具有第一连接部及第二连接部，第一连接部与第二连接部通过基板的内部线路电连接；其中，第二连接部为贯穿基板的通孔，通孔内设置有带有连接孔的电镀层；芯片，芯片设置于基板之上，并与第一连接部电连接，以便第二连接部与芯片之间通过基板的内部线路形成信号通路；保护层，保护层设置于基板上，并将芯片及第二连接部包裹于保护层内，保护层上与第二连接部对应的位置具有过线孔，以便信号线穿过过线孔与第二连接部电连接。本申请实施例提供的技术方案，可减少信号通路上的寄生电容，有效提高接收端的信号质量，提高信号线连接可靠性，且减小体积，降低成本。
摘要（英）：

Provided in embodiments of the present application are a chip packaging structure and a packaging method. The chip packaging structure comprises: a substrate, which is provided with a first connection portion and a second connection portion, the first connection portion being electrically connected to the second connection portion by means of an internal circuit of the substrate, the second connection portion being a through hole penetrating the substrate, and an electroplated layer having connection holes being provided inside the through hole; a chip, which is disposed on the substrate and is electrically connected to the first connection portion, so that a signal pathway is formed between the second connection portion and the chip by means of the internal circuit of the substrate; and a protection layer, which is disposed on the substrate, and in addition, the chip and the second connection portion are wrapped inside the protection layer, a position on the protection layer corresponding to the second connection portion is provided with a wire through hole, such that a signal line passes through the wire through hole to be electrically connected to the second connection portion. The technical solution according to the embodiments of the present application can reduce parasite capacitance on the signal pathway, effectively improve the signal quality of a receiving terminal, improve signal line connection reliability, reduce the volume, and lower the cost.

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