Invention Application
- Patent Title: INTEGRATED CIRCUIT PACKAGE WITH STACKED INTEGRATED CIRCUIT DIES AND METHOD OF FABRICATING THE SAME
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Application No.: PCT/US2021/038033Application Date: 2021-06-18
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Publication No.: WO2022026078A1Publication Date: 2022-02-03
- Inventor: KANG, Kuiwon , KIM, Michelle Yejin , BUOT, Joan Rey Villarba , TONG, Jialing
- Applicant: QUALCOMM INCORPORATED
- Applicant Address: ATTN: International IP Administration
- Assignee: QUALCOMM INCORPORATED
- Current Assignee: QUALCOMM INCORPORATED
- Current Assignee Address: ATTN: International IP Administration
- Agency: TERRANOVA, Steven, N.
- Priority: US17/158,374 2021-01-26
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L25/065 ; H01L23/49 ; H01L21/48
Abstract:
An integrated circuit package has at least two stacked IC dies (204, 206), where a first IC die (204) couples to a metallization structure directly through solder balls (220) and a second IC die (206) stacked on top of the first die (204) connects to the metallization structure through wire bond connections (228(1)-228(X)). The IC dies (204,206) are electrically coupled to one another through an interior metal layer (210(1)) of the metallization structure. Vias (212) are used to couple to the interior metal layer (210(1)). Optionally a third wire bonded IC die may be stacked on the second IC die (206) and electrically coupled to the first IC die through the interior metal layer (210(1))
Information query
IPC分类:
