The present application relates to the technical field of semiconductor manufacturing and provides a manufacturing method for a semiconductor structure and a semiconductor structure, with the aim of solving current problems of a relatively large thermal budget during a semiconductor structure manufacturing process, and an amorphous silicon layer of a furnace tube affecting a work function adjustment process of a work function layer on a transistor. The manufacturing method for a semiconductor structure of the present application comprises forming a first stack layer; arranging a sacrificial layer on the first stack layer; performing thermal annealing on the first stack layer and the sacrificial layer, the first stack layer forming a second stack layer; removing the sacrificial layer and a first conductive layer and a work function composite layer in the second stack layer, and retaining a high dielectric constant layer, a second interface layer, and a substrate in the second stack layer; and forming a gate electrode layer on the high dielectric constant layer. The present application is able to optimize a work function adjustment process of a semiconductor structure, and improve the performance of the semiconductor structure.