Provided in the embodiments of the present application is an error correction system, comprising M decoding units, which are configured to perform decoding processing on X first operation codes and Y second operation codes, wherein each decoding unit comprises: a decoder, which is configured to receive the X first operation codes and output N first decoding signals, with each first decoding signal corresponding to one bit of N pieces of data; a first AND gate unit, which is configured to receive Z selected operation codes and perform logical AND operation; an NOR gate unit, which is configured to receive (Y-Z) unselected operation codes and perform logical NOR operation; and N second AND gate units, wherein an input end of each second AND gate unit is connected to an output end of the first AND gate unit, an output end of the NOR gate unit and one first decoding signal, and error detection and/or error correction are/is performed on a storage system on the basis of outputs of the N second AND gate units.