A chip test circuit and method, which relate to the technical field of chips, and by means of which high-rate test data of a test machine can be received and converted into multi-channel input data by using a high-speed serial test interface, thereby eliminating the limitations on a test data transmission bandwidth of a single channel, and improving the chip test efficiency. The chip test circuit comprises: a high-speed serial test interface, which is used for receiving high-speed serial input data sent by a test machine, converting the high-speed serial input data into multi-channel input data, and sending the multi-channel input data to a first speed changer; the first speed changer, which is used for normalizing the multi-channel input data into single-channel input data so as to test a circuit to be tested; and a second speed changer, which is used for receiving single-channel output data from the circuit to be tested, converting the single-channel output data into multi-channel output data, and outputting the multi-channel output data to the high-speed serial test interface, wherein the high-speed serial test interface is further used for converting the multi-channel output data into high-speed serial output data, and sending same to the test machine.