公开(公告)号：WO2022266959A1

公开(公告)日：2022-12-29

申请号：PCT/CN2021/102190

申请日：2021-06-24

Applicant: 华为技术有限公司

Inventor： 付海涛 ,  黄俊林 ,  邓斌 ,  崔昌明

IPC: G01R31/317 ,  H04B17/00

Abstract: 一种芯片测试电路和方法，涉及芯片技术领域，能够利用高速串行测试接口接收测试机台的高速率测试数据并转换为多通道输入数据，解放单个通道的测试数据传输带宽限制，提升芯片测试效率。该芯片测试电路包括高速串行测试接口，用于接收测试机台发送的高速串行输入数据转换为多通道输入数据，向第一变速器发送多通道输入数据；第一变速器，用于将多通道输入数据归一为单通道输入数据对待测试电路进行测试；第二变速器，用于从待测试电路接收单通道输出数据转换为多通道输出数据输出至高速串行测试接口；高速串行测试接口，还用于将多通道输出数据转换为高速串行输出数据发送给测试机台。

公开(公告)号：WO2022243515A1

公开(公告)日：2022-11-24

申请号：PCT/EP2022/063729

申请日：2022-05-20

Applicant: NORDIC SEMICONDUCTOR ASA

Inventor： PEDERSEN, Frode

IPC: G01R31/317 ,  G06F21/00 ,  G01R31/3181 ,  G06F30/32

Abstract: An integrated circuit comprising a detection circuit portion (102) for detecting an electromagnetic pulse attack on the integrated circuit is provided. The detection circuit portion (102) comprises a shadow flip-flop (106) comprising a clock input and a clock net (126) connected to said clock input. The detection circuit portion (102) also comprises a clock gate (124) connected to the clock net (126), wherein the clock gate (124) is controlled by an enable signal so as selectively to be in an open state in which the clock gate (124) passes a clock signal to the clock net (126) or in a closed state in which the clock gate (124) does not pass the clock signal to the clock net (126). The detection circuit portion (102) further comprises an error circuit portion (117), wherein the error circuit portion (117) is arranged to selectively output an error signal if: the shadow flip-flop (106) is clocked by a signal from the clock net (126) and the clock gate (124) is in the closed state.

公开(公告)号：WO2022169996A1

公开(公告)日：2022-08-11

申请号：PCT/US2022/015151

申请日：2022-02-03

Applicant: TEKTRONIX, INC.

Inventor： PICKERD, John, J. ,  TAN, Kan

IPC: G01R31/317 ,  G01R31/319 ,  G01R31/3193 ,  G01R13/02 ,  H04L1/24

Abstract: A system for generating images on a test and measurement device includes a first input for accepting a waveform input signal carrying sequential digital information and an image generator structured to generate a visual image using a segment of the waveform input only when two or more sequential codes of digital information match sequential codes carried in the sequential digital information of the segment of the waveform input. A user-defined state-machine comparator may be used to determine which segments of the waveform input signal are used in the image generation.

公开(公告)号：WO2022152032A1

公开(公告)日：2022-07-21

申请号：PCT/CN2022/070473

申请日：2022-01-06

Applicant: 深圳比特微电子科技有限公司

Inventor： 陈默 ,  范志军 ,  刘建波 ,  许超

IPC: G01R31/317 ,  G01R31/3183 ,  G11C29/14

Abstract: 一种测试电路(300,300',400,500,600,700,800)包括：测试序列提供模块(301)，用于提供测试序列(PRBS)到待测试的时序器件(303)；时钟驱动模块(307,407,507,607,707,807)，用于提供时钟信号(759)到待测试的时序器件(303)，其包括第一时钟驱动电路(610,710)，第一时钟驱动电路(610,710)包括：多个第一时钟路径(421,423)，分别提供对应的时钟信号(759)；以及逻辑单元(427,715)，基于多个第一时钟路径(421,423)提供的时钟信号(759)中的至少一部分，产生脉宽调节的第一时钟信号以用于待测试的时序器件(303)；以及验证模块(305,405,805)，用于对待测试的时序器件(303)的输出进行验证。

公开(公告)号：WO2022132538A1

公开(公告)日：2022-06-23

申请号：PCT/US2021/062467

申请日：2021-12-08

Applicant: RAMBUS INC.

Inventor： BAMDHAMRAVURI, Srinivas Satish Babu ,  WIJETUNGA, Panduka

IPC: G01R31/317 ,  G11C29/10 ,  G11C29/14 ,  G11C29/16

Abstract: Technologies for signal skew correction in integrated circuit memory devices are described. An integrated circuit memory device includes a first interface to receive command/address (CA) signals and a clock signal, a data interface, and a mode register. During a CA bus loopback mode, the first interface receives a pattern of CA signals and the clock signal and the data interface outputs the pattern of CA signals. During the CA bus loopback mode, the mode register can be programmed with a value representative of a timing offset between the clock signal and a sampling point for the first interface.

公开(公告)号：WO2022117687A1

公开(公告)日：2022-06-09

申请号：PCT/EP2021/083850

申请日：2021-12-01

Applicant: THALES DIS FRANCE SAS

Inventor： TEGLIA, Yannick ,  LOUBET MOUNDI, Philippe ,  GRAVELLIER, Joseph ,  DUTERTRE, Jean-Max

IPC: G01R31/317 ,  G06F11/07 ,  G06F21/60 ,  G06F21/55 ,  G06F21/71 ,  H04L9/00 ,  H04L9/12

Abstract: The invention relates to a system on chip (10, 20) comprising a memory controller (13, 23) having a clock synchronization circuitry based on a locked loop (16, 26). The system on chip further comprises a voltage glitch attack detector (17, 27) configured to monitor a clock synchronization signal generated by the clock synchronization circuitry and check whether the monitored clock synchronization signal is a nominal signal or a signal characteristic of a voltage glitch attack. The voltage glitch attack detector may be a software detector executed by a processing unit.

公开(公告)号：WO2022115495A1

公开(公告)日：2022-06-02

申请号：PCT/US2021/060663

申请日：2021-11-23

Applicant: TEKTRONIX, INC.

Inventor： FROELICH, Daniel, S. ,  STRICKLING, Sam, J.

IPC: G01R31/3161 ,  G01R31/317 ,  G01R31/319 ,  G06F11/273 ,  G06F11/263

Abstract: A system for data creation, storage, analysis, and training while margin testing includes a margin test generator coupled through an interface to a Device Under Test (DUT). The margin test generator is structured to modify test signals for testing the DUT during one or more testing states of a test session to create testing results. The testing results are stored in a data repository along with a DUT identifier of the DUT tested during the test session. A comparator determine whether any results of the DUT test results match a predictive outcome that is based from an analysis of previous DUT tests. If so, a message generator produces an indication that the tested DUT matched the predictive outcome.

公开(公告)号：WO2022103232A1

公开(公告)日：2022-05-19

申请号：PCT/KR2021/016678

申请日：2021-11-15

Applicant: 충남대학교산학협력단

Inventor： 이희덕 ,  송형섭 ,  최현웅

IPC: G01R31/3183 ,  G01R31/317

Abstract: 신소자 테스트 시스템이 개시된다. 상기 시스템은, 하나 이상의 단위 셀 테스트 어레이;를 포함하는 어레이 테스트 패턴; 및 상기 어레이 테스트 패턴에 신호를 인가하기 위한 디멀티플렉서;를 포함할 수 있다. 상기 단위 셀 테스트 어레이는, 트랜지스터;를 포함하고, 상기 트랜지스터에는 BEOL 공정을 통해 테스트 대상이 되는 신소자가 집적될 수 있다.

公开(公告)号：WO2022100756A1

公开(公告)日：2022-05-19

申请号：PCT/CN2021/130951

申请日：2021-11-16

Applicant: 上海唯捷创芯电子技术有限公司

Inventor： 王永寿 ,  高晨阳 ,  林升

IPC: G01R31/317

Abstract: 本发明公开了一种芯片端口状态检测电路、芯片及通信终端。该芯片端口状态检测电路通过端口检测转换电路将待检测端口的状态转换为相应的电压，分别输出到第一比较器和第二比较器，与相应的输入参考电压进行比较后，向芯片ID判断电路输出逻辑信号，得到与芯片待检测端口状态对应的芯片ID，以区分出多颗相同的芯片。另一方面，通过动态偏置电流产生电路在电源电压开始建立到建立完成之前和在电源电压建立完成之后分别为第一比较器和第二比较器提供偏置电流以及静态工作点，不仅实现在通信终端识别芯片之前对芯片的待检测端口状态完成检测，满足对芯片待检测端口快速检测的要求，而且可以满足芯片端口状态检测电路静态低功耗且实时检测的要求。

公开(公告)号：WO2022032526A1

公开(公告)日：2022-02-17

申请号：PCT/CN2020/108708

申请日：2020-08-12

Applicant: 深圳先进技术研究院

Inventor： 赛高乐 ,  欧勇盛 ,  段圣宇 ,  王志扬 ,  徐升 ,  熊荣 ,  刘超 ,  冯伟 ,  吴新宇

IPC: G01R31/317 ,  H03K19/00

Abstract: 一种监测传感器及芯片，其中监测传感器包括，逻辑运算电路（110），逻辑运算电路（110）用于对输入的多个待监测信号进行异或逻辑运算，并输出运算结果信号；其中，待监测信号为数字信号；监测电路（120），监测电路（120）连接逻辑运算电路（110），用于监测运算结果信号的跳变情况，从而对多个监测信号进行监测。通过上述方法，所提供的监测传感器可以对多路数据进行跳变监测，提高了监测效率。