公开(公告)号：EP1807766A2

公开(公告)日：2007-07-18

申请号：EP05731247.2

申请日：2005-03-31

申请人： Analog Devices, Inc.

发明人： HOLLIS, Paul, W. ,  LATTIMORE, George, M. ,  RUTLEDGE, Matthew, B.

IPC分类号： G06F12/00

CPC分类号： G11C7/22 ,  G06F13/1689 ,  G11C7/1072 ,  G11C7/222 ,  G11C2207/2272 ,  G11C2207/2281 ,  G11C2207/229

摘要： A de-coupled memory access system (50) including a memory access control circuit (52) configured to generate first and second independent, de-coupled time references. The memory access control circuit (52) includes a read initiate circuit (54) responsive to the first time reference (58) and a read signal for generating a read-enable signal (66), and a write initiate circuit (58) responsive to the second time reference (60) and a write signal for generating a write enable signal (70) independent of the read enable signal for providing independent, de-coupled write access to a memory array (80).

公开(公告)号：EP1807766B1

公开(公告)日：2014-06-04

申请号：EP05731247.2

申请日：2005-03-31

申请人： Analog Devices, Inc.

发明人： HOLLIS, Paul, W. ,  LATTIMORE, George, M. ,  RUTLEDGE, Matthew, B.

IPC分类号： G11C7/22 ,  G11C7/10 ,  G06F13/16

CPC分类号： G11C7/22 ,  G06F13/1689 ,  G11C7/1072 ,  G11C7/222 ,  G11C2207/2272 ,  G11C2207/2281 ,  G11C2207/229