摘要:
The analog-to-digital converter array 13 includes one analog-to-digital converter 210 for each row of photodetectors 120 in the photodetector array 11. The image-processing unit 14 includes the plurality of processing circuits 400 for performing high-speed image processing. The signal converter 17 combines the output signals from the analog-to-digital converter array 13 with output signals from the image-processing unit 14. Under control of the control circuit 15 and the signal conversion controller 19, the signal converter 17 downconverts the composite signal at an important timing to a frame rate suitable for display on the monitor 18 and subsequently displays the signal on the monitor 18.
摘要:
An A/D converter array (13) has A/D converters (210) each corresponding to each row of photodetector elements (120) of a photodetector array (11). An image-processing unit (14) includes a plurality of processing circuits (400) for high-speed image processing. A signal converter (17) combines the output signal from the A/D converter array (13) and the output signal from the image-processing unit (14). Under control of a control circuit (15) and a signal conversion controller (19), the signal converter (17) downconverts the combined signal at a frame rate suitable for the display of monitor (18), particularly at important timing.
摘要:
A signal image is transmitted by write light from a transmission type liquid crystal element 4 to an optically-addressed type parallel-aligned nematic-liquid-crystal spatial light modulator 6. The numerical aperture NA L of a relay lens 5, the pitch P of the pixel structure of the transmission type liquid crystal element 4, and the wavelength λ of light from the write light source 1 are set with the condition 1/2P L /λ . As a result, the signal component caused by the pixel structure can be erased. Furthermore, no degradation is generated in the entire range of the spatial frequencies of the signal image that can be produced by the transmission type liquid crystal element 4.
摘要:
There is provided a solid-state imaging device in which images can be read at high speed. Since an n-th processing circuit (e.g. PU1) can be connected to n-th pixel columns (N1) in respective imaging blocks B1, B2, and B3 via switches Q (1), Q (4), and Q (7), signals from the adjacent pixel columns (N2) are to be processed separately by another processing circuit (PU2) even when a partial readout area R may be small. In addition, an image data arithmetic section 10 specifies the partial readout area R restrictively, which allows for higher speed imaging.
摘要:
A high-speed vision sensor comprises an analog-to-digital converter array (13) including analog-to-digital converters (210) corresponding to respective lines of photodetectors (120) of a photodetector array (11), and a parallel processing system (14) consisting of processing elements (400) and shift registers (410) corresponding to the respective photodetectors (120). Since processing elements (400) carry out the image processing between adjacent pixels by parallel processing at high speed, independently of the operation in the shift registers (410), the processing and shifting can be performed efficiently.
摘要:
N photodetectors (80 1-80N) each comprise a photo diode (PD), a capacitor (C d), and a switch (SW 0). An integrator circuit (10) includes a parallel circuit of an amplifier (A 1), a capacitor (C f1) and a switch (SW 11) between an input terminal and an output terminal. The capacitance of the capacitor (C f1) is equal to the capacitance of each capacitor (Cd) of the photodetectors (80 1-80N). A switch (SW 01) is provided between the switches (SW 0) of the photodetectors (80 1-80N) and the input terminal of the integrator circuit (10). A switch (SW 02) is provided between the output terminal of the integrator circuit (10) and the switches (SW 0) of the photodetectors (80 1-80N).
摘要:
There is provided a solid-state imaging device in which images can be read at high speed. Since an n-th processing circuit (e.g. PU1) can be connected to n-th pixel columns (N1) in respective imaging blocks B1, B2, and B3 via switches Q (1), Q (4), and Q (7), signals from the adjacent pixel columns (N2) are to be processed separately by another processing circuit (PU2) even when a partial readout area R may be small. In addition, an image data arithmetic section 10 specifies the partial readout area R restrictively, which allows for higher speed imaging.