公开(公告)号：EP4002136A1

公开(公告)日：2022-05-25

申请号：EP21198323.4

申请日：2021-09-22

申请人： INTEL Corporation

发明人： COURY, Bassam ,  SEN, Sujoy ,  WILLIS, Thomas ,  SRIVASTAVA, Durgesh

IPC分类号： G06F13/38 ,  G06F12/02 ,  H04L41/0816 ,  H04L41/0896 ,  H04L47/765 ,  G06F13/16

摘要： Examples described herein includes a network interface controller comprising a memory interface and a network interface, the network interface controller configurable to provide access to local memory and remote memory to a requester, wherein the network interface controller is configured with an amount of memory of different memory access speeds for allocation to one or more requesters. In some examples, the network interface controller is to grant or deny a memory allocation request from a requester based on a configuration of an amount of memory for different memory access speeds for allocation to the requester. In some examples, the network interface controller is to grant or deny a memory access request from a requester based on a configuration of memory allocated to the requester. In some examples, the network interface controller is to regulate quality of service of memory access requests from requesters.

公开(公告)号：EP4049123A1

公开(公告)日：2022-08-31

申请号：EP20878684.8

申请日：2020-09-25

申请人： Intel Corporation

发明人： SEN, Sujoy ,  WILLIS, Thomas E. ,  SRIVASTAVA, Durgesh ,  COURY, Bassam N. ,  FAW, Donald L. ,  CINTRA, Marcelo ,  DUGAST, Francois

IPC分类号： G06F3/06 ,  G06F12/084 ,  G06F12/1027 ,  G06F13/38

公开(公告)号：EP4248618A1

公开(公告)日：2023-09-27

申请号：EP21895303.2

申请日：2021-09-21

申请人： INTEL Corporation

发明人： SEN, Sujoy ,  WILLIS, Thomas E. ,  SRIVASTAVA, Durgesh ,  CINTRA, Marcelo ,  COURY, Bassam N.

IPC分类号： H04L12/18 ,  H04L12/54

公开(公告)号：EP4002134A1

公开(公告)日：2022-05-25

申请号：EP21196829.2

申请日：2021-09-15

申请人： INTEL Corporation

发明人： SEN, Sujoy ,  SRIVASTAVA, Durgesh ,  WILLIS, Thomas E. ,  COURY, Bassam N. ,  CINTRA, Marcelo

IPC分类号： G06F13/28

摘要： Examples described herein include one or more processors; a network interface; and a direct memory access (DMA) engine communicatively coupled to the one or more processors. In some examples, the DMA engine is to receive a DMA data access request and based on an address in the DMA data access request corresponding to a remote memory device, the DMA engine is to cause the network interface to generate at least one packet for transmission to the remote memory device. In some examples, the DMA data access request includes a source address, a destination address, and a length. In some examples, if the source address corresponds to a local memory device and the destination address corresponds to a remote memory device, the DMA engine is to cause the network interface to generate at least one packet for transmission to the remote memory device, wherein the at least one packet includes data stored at the source address.