公开(公告)号：EP3488352A1

公开(公告)日：2019-05-29

申请号：EP17831476.1

申请日：2017-06-14

申请人： INTEL Corporation

发明人： WAGH, Mahesh ,  MYERS, Mark S. ,  VAN DOREN, Stephen R. ,  ZIAKAS, Dimitrios ,  COURY, Bassam

IPC分类号： G06F13/42

公开(公告)号：EP4002136A1

公开(公告)日：2022-05-25

申请号：EP21198323.4

申请日：2021-09-22

申请人： INTEL Corporation

发明人： COURY, Bassam ,  SEN, Sujoy ,  WILLIS, Thomas ,  SRIVASTAVA, Durgesh

IPC分类号： G06F13/38 ,  G06F12/02 ,  H04L41/0816 ,  H04L41/0896 ,  H04L47/765 ,  G06F13/16

摘要： Examples described herein includes a network interface controller comprising a memory interface and a network interface, the network interface controller configurable to provide access to local memory and remote memory to a requester, wherein the network interface controller is configured with an amount of memory of different memory access speeds for allocation to one or more requesters. In some examples, the network interface controller is to grant or deny a memory allocation request from a requester based on a configuration of an amount of memory for different memory access speeds for allocation to the requester. In some examples, the network interface controller is to grant or deny a memory access request from a requester based on a configuration of memory allocated to the requester. In some examples, the network interface controller is to regulate quality of service of memory access requests from requesters.

公开(公告)号：EP3879410A1

公开(公告)日：2021-09-15

申请号：EP21168844.5

申请日：2017-06-14

申请人： INTEL Corporation

发明人： WAGH, Mahesh ,  MYERS, Mark S. ,  VAN DOREN, Stephen R. ,  ZIAKAS, Dimitrios ,  COURY, Bassam

IPC分类号： G06F13/38

摘要： The present disclosure provides an apparatus comprising a plurality of processing cores integrated onto multiple integrated circuit dies in a package, the plurality of processing cores to execute instructions and process data, memory logic to couple to a memory device, a coherent interconnect fabric to connect the plurality of processing cores and the memory logic and a physical, PHY, layer interface. The physical, PHY, layer interface comprising a plurality of connectors coupled to a plurality of data lanes, the plurality of connectors including a first subset of the connectors to communicate in accordance with a first interconnect protocol, a second subset of the connectors to communicate in accordance with a second interconnect protocol, and a third subset of the connectors to communicate in accordance with a third interconnect protocol. The apparatus comprising a first logical sub-block to encode data in accordance with the first interconnect protocol, a second logical sub-block to encode data in accordance with the second interconnect protocol and a third logical sub-block to encode data in accordance with the third interconnect protocol and a multiplexer. The multiplexer is to connect the first subset of connectors to the first logical sub-block, to connect the second subset of the connectors to the second logical sub-block, and to connect the third subset of the connectors to the third logical sub-block. The apparatus comprising a first transaction layer to communicate data between the coherent interconnect fabric and the first logical sub-block in accordance with the first interconnect protocol; a second transaction layer to communicate data between the coherent interconnect fabric and the second logical sub-block in accordance with the second interconnect protocol; and a third transaction layer to communicate data between the coherent interconnect fabric and the third logical sub-block in accordance with the third interconnect protocol.