公开(公告)号：EP1141834B1

公开(公告)日：2002-09-04

申请号：EP99966804.9

申请日：1999-12-01

申请人： Infineon Technologies AG

发明人： HÖNIGSCHMID, Heinz ,  BRAUN, Georg ,  MAJDIC, Andrej

IPC分类号： G06F11/20

CPC分类号： G11C29/78 ,  G11C29/702

摘要： The invention relates to an IC memory with a normal bit line (BL) for transmitting data from or to normal memory cells (MC) connected to said line. The IC memory is further provided with a normal sense amplifier (SA1) which is linked via a line (L1) at the one end with the normal bit line (BL) and at the other end with a data line (DQ1). Said sense amplifier amplifies the data read out from the normal memory cells (MC). The memory also comprises a redundant sense amplifier (RSA1) for replacing the normal sense amplifier (SA1) in the case of a redundancy. Said redundant sense amplifier is also linked at the one end with the line (L1) and at the other end with the data line (DQ1) and amplifies the data read out from the normal memory cells (MC) in the case of a redundancy.

摘要翻译： 具有正常位线（BL）的IC存储器本发明涉及一种具有正常位线（BL）的IC存储器，用于从连接到所述线路的正常存储单元（MC）发送数据或向正常存储单元 IC存储器进一步配备有经由线路（L1）在一端与正常位线（BL）连接并且在另一端与数据线路（DQ1）连接的常规感测放大器（SA1）。 所述读出放大器放大从正常存储单元（MC）读出的数据。 存储器还包括冗余读出放大器（RSA1），用于在冗余情况下替换常规读出放大器（SA1）。 所述冗余读出放大器在一端与线（L1）连接，另一端与数据线（DQ1）连接，并且在冗余情况下放大从正常存储单元（MC）读出的数据。

公开(公告)号：EP1141834A1

公开(公告)日：2001-10-10

申请号：EP99966804.9

申请日：1999-12-01

申请人： Infineon Technologies AG

发明人： HÖNIGSCHMID, Heinz ,  BRAUN, Georg ,  MAJDIC, Andrej

IPC分类号： G06F11/20

CPC分类号： G11C29/78 ,  G11C29/702

摘要： The invention relates to an IC memory with a normal bit line (BL) for transmitting data from or to normal memory cells (MC) connected to said line. The IC memory is further provided with a normal sense amplifier (SA1) which is linked via a line (L1) at the one end with the normal bit line (BL) and at the other end with a data line (DQ1). Said sense amplifier amplifies the data read out from the normal memory cells (MC). The memory also comprises a redundant sense amplifier (RSA1) for replacing the normal sense amplifier (SA1) in the case of a redundancy. Said redundant sense amplifier is also linked at the one end with the line (L1) and at the other end with the data line (DQ1) and amplifies the data read out from the normal memory cells (MC) in the case of a redundancy.