公开(公告)号：EP1163675B1

公开(公告)日：2003-11-05

申请号：EP00918694.1

申请日：2000-03-10

申请人： Infineon Technologies AG

发明人： BÖHM, Thomas ,  BRAUN, Georg ,  HÖNIGSCHMID, Heinz ,  MANYOKI, Zoltan ,  RÖHR, Thomas

IPC分类号： G11C7/14 ,  G11C11/22

CPC分类号： G11C11/22 ,  G11C7/14

摘要： The inventive memory has identically structured memory cells (MC) and reference cells (RC). Reference information is written into the reference cells (RC) by means of the reference cells (RC) being uncoupled from the read amplifiers (SAi) with first switching elements (S1) and the part of the bit lines (BLi, bBLi) that is connected to the reference cells (RC) being electrically connected to a potential line (P1) that conducts the reference information with second switching elements (S2).

公开(公告)号：EP1119858B1

公开(公告)日：2003-02-05

申请号：EP99950445.9

申请日：1999-07-28

申请人： Infineon Technologies AG

发明人： RÖHR, Thomas ,  HÖNIGSCHMID, Heinz ,  MANYOKI, Zoltan ,  BÖHM, Thomas ,  NEUHOLD, Ernst ,  BRAUN, Georg

IPC分类号： G11C8/00 ,  H03K19/094

CPC分类号： G11C5/143 ,  G11C8/08 ,  G11C16/12 ,  H03K19/09425 ,  H03M5/16

摘要： The decoder element (DE) is provided with an output (WLi), whereby an output signal with three different potentials (-2 volts, 0 volts, 4 volts) is produced. The output signal is produced according to input signals at the terminal connections (1, 2, 3) of the decoder element (DE).

公开(公告)号：EP1232528A2

公开(公告)日：2002-08-21

申请号：EP00966118.2

申请日：2000-10-05

申请人： Infineon Technologies AG

发明人： HÖNIGSCHMID, Heinz ,  BRAUN, Georg

IPC分类号： H01L27/108

CPC分类号： H01L27/10885 ,  G11C5/10 ,  H01L27/10811 ,  H01L27/10814

摘要： The invention relates to a memory device comprising numerous memory cells, each cell comprising at least one selection transistor and one stacked capacitor and being driven via word (3) and bit lines (14, 16). Said memory device is characterised in that the bit lines (14, 16) are led through two metallised sheets and in that the stacked capacitors (7, 8, 9) of the memory cells are located between these metallised sheets.

公开(公告)号：EP1393173A1

公开(公告)日：2004-03-03

申请号：EP02726088.4

申请日：2002-05-13

申请人： Infineon Technologies AG

发明人： BENEDIX, Alexander ,  BRAUN, Georg ,  KLEHN, Bernd

IPC分类号： G06F9/46 ,  G06F13/16

CPC分类号： G06F11/3409

摘要： The invention relates to a configuration for executing data processing processes comprising an operating system (1) and different system resources (2) which are accessed by the operating system (1) using an access strategy for executing system processes. According to the invention, different access strategies (A, B, C, ) for accessing the system resources (2) can be used in different applications (3, 3'). The invention also relates to a method for determining the optimal access strategies (A, B, C, ) for accessing the system resources (2).

公开(公告)号：EP1103051B1

公开(公告)日：2003-04-23

申请号：EP99945910.0

申请日：1999-07-05

申请人： Infineon Technologies AG

发明人： BRAUN, Georg ,  HÖNIGSCHMID, Heinz

IPC分类号： G11C11/22

CPC分类号： H01L27/11502 ,  G11C11/22

摘要： The invention relates to a ferroelectric storage assembly containing a storage cell array comprised of a plurality of storage cells. Each storage cell comprises at least one selector transistor (TG1, TG2) and one storage capacitor (CF1, CF2) and can be controlled via word lines (WL) and bit lines (BL, bBL). A short-circuit transistor (SG1, SG2) is located over each storage capacitor (CF1, CF2) in order to protect the storage capacitor (CF1, CF2) from disturbing pulses.

公开(公告)号：EP1088309B1

公开(公告)日：2002-09-18

申请号：EP99938150.2

申请日：1999-06-09

申请人： Infineon Technologies AG

发明人： BRAUN, Georg

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： The inventive method makes it possible to reduce or prevent modifications of the hysteresis curve as a result of alteration of the ferromagnetic material in ferroelectric memories in that the complementary state is also written and the capacitor voltage is lowered to 0V before the memory cell is deactivated during reading and writing.

公开(公告)号：EP1163679A1

公开(公告)日：2001-12-19

申请号：EP00912402.5

申请日：2000-03-02

申请人： Infineon Technologies AG

发明人： BÖHM, Thomas ,  BRAUN, Georg

IPC分类号： G11C29/00

CPC分类号： G11C29/52

摘要： Before a write and/or read access to one of the memory cells is carried out, a security information stored in a security memory cell is read out. If the security information is characterized by a first logic state an error signal is generated. If the read-out security information is characterized by a second logic state the memory cell is accessed and a write access is carried out to the security memory cell during which a new security information to be he stored having the second logic state is written to the cell.

公开(公告)号：EP1138084A1

公开(公告)日：2001-10-04

申请号：EP99963195.5

申请日：1999-11-03

申请人： Infineon Technologies AG

发明人： HANEDER, Thomas-Peter ,  WILLER, Josef ,  BRAUN, Georg ,  SCHLÖSSER, Till

IPC分类号： H01L29/78 ,  H01L29/51

CPC分类号： H01L29/78391

摘要： A ferroelectric transistor with two source/drain areas (2) and a channel area (3) arranged therebetween in a semiconductor substrate (1). A metal intermediate layer (4) is disposed on the surface of the channel area (3) whereby said intermediate layer forms a Schottky diode with the semiconductor substrate (1) and a ferroelectric layer (5) and a gate electrode (6) are arranged on the surface thereof. The ferroelectric transistor is produced in various steps using silicon process technology.

公开(公告)号：EP1118080A1

公开(公告)日：2001-07-25

申请号：EP99948705.1

申请日：1999-07-28

申请人： Infineon Technologies AG

发明人： RÖHR, Thomas ,  HÖNIGSCHMID, Heinz ,  MANYOKI, Zoltan ,  BÖHM, Thomas ,  BRAUN, Georg ,  NEUHOLD, Ernst

IPC分类号： G11C8/00

CPC分类号： H03M5/16

摘要： The decoder element (DE) is used to produce an output signal with three different potentials (-2 v, 0 v, 4 v) at an output (WLi). The second potential (0 v) is located between the first (-2 v) and the third (4 v) potential. The decoder element (DE) enables any of the three potentials (-2 v, 0 v, 4 v) to be produced at the output (WLi) according to the potentials at the terminal connections of said decoder element.

公开(公告)号：EP1103051A1

公开(公告)日：2001-05-30

申请号：EP99945910.0

申请日：1999-07-05

申请人： Infineon Technologies AG

发明人： BRAUN, Georg ,  HÖNIGSCHMID, Heinz

IPC分类号： G11C11/22

CPC分类号： H01L27/11502 ,  G11C11/22

摘要： The invention relates to a ferroelectric storage assembly containing a storage cell array comprised of a plurality of storage cells. Each storage cell comprises at least one selector transistor (TG1, TG2) and one storage capacitor (CF1, CF2) and can be controlled via word lines (WL) and bit lines (BL, bBL). A short-circuit transistor (SG1, SG2) is located over each storage capacitor (CF1, CF2) in order to protect the storage capacitor (CF1, CF2) from disturbing pulses.