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    Improved duplicated circuit arrangement for fast transmission and repairability
    2.
    发明公开
    Improved duplicated circuit arrangement for fast transmission and repairability 失效
    Gedoppelte Schaltungsanordnung zur schnellenÜbertragungund Reparierbarkeit。

    公开(公告)号：EP0273081A1

    公开(公告)日：1988-07-06

    申请号：EP86430056.1

    申请日：1986-12-30

    申请人： International Business Machines Corporation

    发明人： Bauge, Michel ,  Mollier, Pierre ,  Yamour, Yiannis John ,  Boudon, Gérard ,  Peter, Jean-Luc

    IPC分类号： G06F13/40 ,  G06F11/16

    CPC分类号： G06F11/16

    摘要： Duplicated circuit arrangement comprising a main processor (30) and its P bit data bus (44), and two identical redundant devices (21 ; 22), each device is comprised of a processing element (23 ; 35) performing the same task in parallel on a P bits word, and send/receive circuits (24,25;36,37) controlled by the main processor through lines (SR11 to SR22) to transmit said word to and from said main processor. For each device, the send/receive circuits are split into two parts. Send/receive circuit of the first device (21) is split in two parts (24, 25); the first part (24) handles the P/2 Most Significant Bits (MSB's) and the second part (25) handles the P/2 Less Significant Bits (LSB's). In normal operation, during the transmission step, only the first part (24) is allowed to send bits on one half (33) of the data bus (44). Symmetrically send/receive circuit of the second device (22), is also split in two parts (36, 37); the first section (36) handles the P/2 Most Significant bits (MSB's) and the second part (37) handles the P/2 Less Significant Bits (LSB's); only the second part (37) is allowed to send bits on the other half (34) of the data bus (44). Therefore, the data bus driving effort is equally shared between the two devices, the maximum number of simultaneous switching is P/2 for each device. This reduction allows greater transmission speed on large busses.

    摘要翻译： 包括主处理器（30）及其P位数据总线（44）以及两个相同的冗余设备（21; 22）的重复电路装置，每个设备由并行执行相同任务的处理元件（23; 35） 以及由主处理器通过线路（SR11至SR22）控制的发送/接收电路（24,25; 36,37），以将所述单词传送到所述主处理器和从所述主处理器发送所述单词。 对于每个设备，发送/接收电路分为两部分。 第一装置（21）的发送/接收电路分为两部分（24,25）; 第一部分（24）处理P / 2最高有效位（MSB），第二部分（25）处理P / 2较低有效位（LSB）。 在正常操作中，在传输步骤期间，仅允许第一部分（24）在数据总线（44）的一半（33）上发送位。 第二装置（22）的对称发送/接收电路也分成两部分（36,37）; 第一部分（36）处理P / 2最高有效位（MSB），第二部分（37）处理P / 2较低有效位（LSB）; 只有第二部分（37）被允许在数据总线（44）的另一半（34）上发送位。 因此，数据总线驱动力在两台设备之间平均共享，每个设备的最大同时切换次数为P / 2。 这种减少允许大型总线上的传输速度更大。