利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

6 条记录 (耗时 0.012 秒)

    Device for controlling the enqueuing and dequeuing operations of messages in a memory
    2.
    发明公开
    Device for controlling the enqueuing and dequeuing operations of messages in a memory 失效
    在einem Speicher的Vorrichtung zur Nachrichtenwarteschlangenbetriebssteuerung。

    公开(公告)号：EP0418447A1

    公开(公告)日：1991-03-27

    申请号：EP89480145.5

    申请日：1989-09-20

    申请人： International Business Machines Corporation

    发明人： Lips, Jean-Pierre ,  Millet, Jean-Marc ,  Naudin, Bernard

    IPC分类号： G06F5/06

    CPC分类号： G06F5/12 ,  G06F2205/064 ,  G06F2205/123

    摘要： The subject device manages the access to message queues in a memory (6) by an enqueuer 2 and a degiieuer 7 when the enqueuer has priority over the dequeuer. It solves the contention problem raised when the dequeuer dequeues the last message from a queue while the enqueuer is enqueuing a new one. A queue control block QCB and queue status bits E, A, D are assigned to each queue and stored in memories 20 and 22. Each time dequeuer 7 performs a dequeuing operation it sets its D bit (dequeuer active) before updating the queue head field in the QCB block. When the enqueuer performs an enqueuing operation it sets an abort bit A, if it founds the D bit active and E bit active indicating that the queue contains at least one message to warn the dequeuer that it has to abort its proces if it is dequeuing the last message from the queue.

    摘要翻译： 当进入者优先于排队者时，主体设备管理由进入者2和排气装置7对存储器（6）中的消息队列的访问。 它解决了当排队队列新队列时，队列将最后一个消息从队列中队列出来时引发的争用问题。 队列控制块QCB和队列状态位E，A，D被分配给每个队列并存储在存储器20和22中。每当出队员7执行出队操作时，在更新队列头域之前设置其D位（出队活动） 在QCB块中。 当进位队列执行排队操作时，如果发现D位有效，并且E位有效，则表明该队列至少包含一个消息以警告dequeuer必须中止其进程（如果该队列出队） 队列中的最后一条消息。

    Method and apparatus for transferring messages between source and destination users through a shared memory
    4.
    发明公开
    Method and apparatus for transferring messages between source and destination users through a shared memory 失效
    用于通过按比例共享存储器的源和目的地之间的用户消息传输方法和装置。

    公开(公告)号：EP0365731A1

    公开(公告)日：1990-05-02

    申请号：EP88480067.3

    申请日：1988-10-28

    申请人： International Business Machines Corporation

    发明人： Calvignac, Jean ,  Lips, Jean-Pierre ,  Millet, Jean-Marc ,  Munier, Jean-Marie ,  Naudin, Bernard

    IPC分类号： G06F15/16

    CPC分类号： G06F15/167 ,  G06F9/544

    摘要： The memory comprises a linear space and a buffered space, each page of the buffered space is divided in a number m+1 of buffers of equal capacity, with m buffers devoted to the storage of data and one control buffer divided into m control blocks. There is a fixed relationship between one buffer control block and one data buffer. The control blocks are devoted to the storage of buffer and message chaining information. The linear space comprises queue control blocks, with one queue control block per user.
    The messages are received by memory interface 22 from the source users and then are enqueued in link inbound queues (LIQ) which are dynamically built by taking buffers from the buffered space, chaining the buffers by writing buffer and message chaining information in the corresponding buffer control blocks and writing the queue head and queue tail addresses in the user queue control block.
    A centralized control means is designed to process enqueue, dequeue and release orders upon requests from a user selected by an arbitrating means.
    When a link inbound queue becomes not empty, the memory interface 22 sends a dequeue order request to the centralized control means, said request identifying the corresponding user queue control block. The message address is provided in response thereto with the identification of the queue control block of the destination user. Then, the memory interface 22 sends an enqueue request to the centralized control means, said request identifying the address of the message to be enqueued and the queue control block of the destination user. The processing of this enqueue request by the centralized control means causes the messages to be enqueued in an outbound queue from which it is transferred to the destination user, by memory interface 22.

    摘要翻译： 该存储器包括一个线性空间和缓冲空间，所述缓冲空间的每一页被分成相等的容量的缓冲器的数目m ​​+ 1，用专门的数据和一个控制缓冲器划分为m个控制块的存储m个缓冲器。 有一个缓冲控制块和一个数据缓冲器之间的固定关系。 该控制块是专门的缓冲器和消息链接信息的存​​储。 线性空间包括队列的控制块，与每个用户一个队列控制块。 该消息由存储器接口22从源用户接收，然后在其中动态地通过取从缓冲空间缓冲液，通过在相应的缓冲器控制写入缓冲器和消息链接信息链接的缓冲器内置链路入站队列（LIQ）中排队 块和写入队列头和队尾地址在用户队列控制块。 集中式控制装置被设计为处理入队，出队并通过仲裁上手段选择的用户释放时请求的订单。 当链路入站队列变为不为空，存储器接口22发送出队订单请求向集中控制装置，所述请求识别对应的用户队列的控制块。 消息地址是响应与目的地用户的队列控制块的标识向其提供。 然后，存储器接口22发送到排队请求到所述的集中控制装置，所述请求识别要排队的消息和目的地用户的队列控制块的地址。 由集中控制装置使所述消息在从其转移到目标用户队列的出站被排队该排队请求的处理时，通过存储器接口22日

    Mechanism for performing the steady state and error recovery functions of a communication protocol
    6.
    发明公开
    Mechanism for performing the steady state and error recovery functions of a communication protocol 失效
    机构用于执行稳态操作和Fehlerbeseitungsfunktionen的通信协议。

    公开(公告)号：EP0470320A1

    公开(公告)日：1992-02-12

    申请号：EP90480114.9

    申请日：1990-08-10

    申请人： International Business Machines Corporation

    发明人： Beaulieu, Cesca Joseph ,  Calvignac, Jean Louis ,  Millet, Jean-Marc ,  Naudin, Bernard

    IPC分类号： H04L29/06 ,  H04L1/16

    CPC分类号： H04L1/1874 ,  H04L1/1635 ,  H04L29/06

    摘要： The mechanism of the subject invention provides for an efficient interface between the hardware parts and software parts of communication modules used in a communication node wherein one module communicates with another module through a very high speed communication media. It insures the integrity of the data messages transferred between modules without impairing the performance of the data transfers.
    To deal with the problem of data message integrity at a very high speed, data link control DLC protocol relevant to steady state functions is implemented in hardware by finite state machines in the data store interfaces 14 and software running in microprocessor 16 is in charge of the initialization and recovery procedures.The steady functions are implemented by the hardware using sets of indicators in a request table which are representative of the transfer conditions, control blocks SCB which are representative of the transmission protocol variables and a message parameter/status field to carry the xmission protocol variables relevant to the message to the destination node. If an error is detected by the hardware part the indicators allows to freeze the operations of the hardware in order the microprocessor performs the error recovery functions using the transmission protocol variables in the control blocks.

    摘要翻译： 本主题发明的机构提供用于在worin一个模块通过一个非常高速的通信介质与另一模块进行通信的通信节点中使用的硬件部件和通信模块软件部件之间的有效接口。 它确保模块之间传送，而不损害数据传输的性能的数据的消息的完整性。 为了处理数据消息的完整性的麻烦以非常高的速度，相关的稳态功能的数据链路控制DLC协议以硬件实现由有限状态机在所述数据存储接口14和软件在微处理器16上运行是在充电 初始化和恢复procedures.The稳定功能是通过使用套在请求表指标具有代表性的转移条件的硬件实现，控制块SCB具有代表性的传输协议变量和一个消息参数/状态字段来承载 发送何时协议变量相关的消息发送到目的地节点。 如果在错误由硬件部检测出的指标允许冻结硬件的操作，以便所述微处理器执行使用控制块的传输协议变量中的错误恢复功能。