PROCESSING PIPELINE WITH ZERO LOOP OVERHEAD
    1.
    发明公开

    公开(公告)号:EP4414855A3

    公开(公告)日:2024-10-02

    申请号:EP24185320.9

    申请日:2021-09-14

    申请人: INTEL Corporation

    IPC分类号: G06F9/54 G06F15/167 G06F9/38

    摘要: A processing pipeline may include: a first processor associated with a first memory; and a second processor associated with a second memory, the second processor being operably coupled to the first processor via a data interface and being configured downstream from the first processor in the processing pipeline, wherein the first processor and the second processor are capable of processing data blocks in accordance with a plurality of data processing loop iterations associated with a commonly-executed function, wherein the first processor is capable of processing a data block in accordance with a first one of the plurality of data processing loop iterations to provide a processed data block, and storing the processed data block in the first memory, wherein the second processor is capable of receiving the processed data block based upon the processed data block being stored in the first memory, wherein the second processor is capable of processing the processed data block in accordance with a second one of the plurality of data processing loop iterations and storing a result of processing the processed data block in the second memory, and wherein the first processor and the second processor are each capable of processing the data block and the processed data block, respectively, as part of a continuous execution of the first and the second ones of the plurality of data processing loop iterations associated with the commonly-executed function.

    MULTIPLE STORAGE DEVICES IMPLEMENTED USING A COMMON CONNECTOR

    公开(公告)号:EP3382567A1

    公开(公告)日:2018-10-03

    申请号:EP18154453.7

    申请日:2018-01-31

    申请人: INTEL Corporation

    IPC分类号: G06F13/38

    摘要: Provided are an apparatus, system, and method relating to detecting, during a system boot operation, whether a device arranged to implement a first bus interface protocol is coupled to a system through a connector. A bus clock is programmed to be off in response to detection of no device implementing the first bus interface protocol being coupled to the system through the connector. After the bus clock is programmed to be off, a buffer is reprogrammed to assume that the connector implements a second bus interface protocol coupled to a storage device. After reprogramming the buffer, the apparatus, system, and method detect whether a device arranged to implement the second bus interface protocol is coupled to the connector, and the device arranged to implement the second bus interface protocol is initialized in response to detection that the device is coupled to the connector. Other embodiments are described and claimed.

    PEER-TO-PEER STREAMING AND API SERVICES FOR PLURAL APPLICATIONS

    公开(公告)号:EP2243254B1

    公开(公告)日:2018-07-18

    申请号:EP07855748.5

    申请日:2007-12-21

    申请人: Intel Corporation

    摘要: Embodiments of apparatuses with a universal P2P service platform are disclosed herein. A unified infrastructure is built in such apparatuses and a unified P2P network may be established with such apparatuses. In various embodiments, such an apparatus comprises a P2P operating system (OS) virtual machine (VM) 202 and a client guest operating system (OS) virtual machine (VM) 204. There is a collection of P2P services in the P2P OS VM 202 and this VM 202 works as a peer node in the P2P network. There is a collection of API services in the client guest OS VM 204 and this VM 204 interacts with various P2P applications. The two VMs communicate with each other via a shared memory 216 and a virtual machine manager 214. In various embodiments, the apparatus further includes a security checker 318 located in the P2P OS VM 302. Other embodiments are also described.