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公开(公告)号:EP4414855A3
公开(公告)日:2024-10-02
申请号:EP24185320.9
申请日:2021-09-14
申请人: INTEL Corporation
IPC分类号: G06F9/54 , G06F15/167 , G06F9/38
CPC分类号: G06F9/544 , G06F15/167 , G06F9/38873
摘要: A processing pipeline may include: a first processor associated with a first memory; and a second processor associated with a second memory, the second processor being operably coupled to the first processor via a data interface and being configured downstream from the first processor in the processing pipeline, wherein the first processor and the second processor are capable of processing data blocks in accordance with a plurality of data processing loop iterations associated with a commonly-executed function, wherein the first processor is capable of processing a data block in accordance with a first one of the plurality of data processing loop iterations to provide a processed data block, and storing the processed data block in the first memory, wherein the second processor is capable of receiving the processed data block based upon the processed data block being stored in the first memory, wherein the second processor is capable of processing the processed data block in accordance with a second one of the plurality of data processing loop iterations and storing a result of processing the processed data block in the second memory, and wherein the first processor and the second processor are each capable of processing the data block and the processed data block, respectively, as part of a continuous execution of the first and the second ones of the plurality of data processing loop iterations associated with the commonly-executed function.
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公开(公告)号:EP4409494A1
公开(公告)日:2024-08-07
申请号:EP22877101.0
申请日:2022-09-02
IPC分类号: G06Q10/10 , G06F15/173
CPC分类号: G06F9/544
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公开(公告)号:EP4377806A1
公开(公告)日:2024-06-05
申请号:EP22850259.7
申请日:2022-07-27
申请人: INTEL Corporation
发明人: SANKARAN, Rajesh M. , LANTZ, Philip R. , JOSHI, Dhananjay A. , RANGANATHAN, Narayan , KHOR, Hai Ming , KUMAR, Sanjay , RAO, Nikhil , GAYEN, Saurabh , KAKAIYA, Utkarsh Y.
IPC分类号: G06F12/1027 , G06F3/06 , G06F15/78
CPC分类号: G06F9/544
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公开(公告)号:EP4364059A1
公开(公告)日:2024-05-08
申请号:EP22833882.8
申请日:2022-06-10
发明人: KAZAKOV, Maxim V.
CPC分类号: G06F9/544 , G06N3/04 , G06N3/063 , G06F9/3012 , G06F9/3001
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公开(公告)号:EP4356242A1
公开(公告)日:2024-04-24
申请号:EP22735345.5
申请日:2022-06-09
发明人: ALBARAKAT, Laith , BRADBURY, Jonathan , SLEGEL, Timothy , LICHTENAU, Cedric , WEISHAUPT, Simon , SAPORITO, Anthony
CPC分类号: G06F9/3877 , G06F9/30036 , G06F9/30076 , G06F9/30014 , G06F9/544 , G06F9/3887 , G06N3/105
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公开(公告)号:EP3382567A1
公开(公告)日:2018-10-03
申请号:EP18154453.7
申请日:2018-01-31
申请人: INTEL Corporation
IPC分类号: G06F13/38
CPC分类号: G06F13/4221 , G06F9/544 , G06F13/385 , G06F13/4234 , G06F13/4291 , G06F2213/0026 , G06F2213/0032
摘要: Provided are an apparatus, system, and method relating to detecting, during a system boot operation, whether a device arranged to implement a first bus interface protocol is coupled to a system through a connector. A bus clock is programmed to be off in response to detection of no device implementing the first bus interface protocol being coupled to the system through the connector. After the bus clock is programmed to be off, a buffer is reprogrammed to assume that the connector implements a second bus interface protocol coupled to a storage device. After reprogramming the buffer, the apparatus, system, and method detect whether a device arranged to implement the second bus interface protocol is coupled to the connector, and the device arranged to implement the second bus interface protocol is initialized in response to detection that the device is coupled to the connector. Other embodiments are described and claimed.
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公开(公告)号:EP3365769A1
公开(公告)日:2018-08-29
申请号:EP16857989.4
申请日:2016-10-05
申请人: KnuEdge, Inc.
发明人: PALMER, Douglas A. , WHITE, Andrew
IPC分类号: G06F9/30 , G06F9/302 , G06F9/318 , G06F9/32 , G06F9/34 , G06F9/38 , G06F9/44 , G06F12/08 , G06F15/16 , G06F15/78
CPC分类号: G06F9/30098 , G06F9/3012 , G06F9/3016 , G06F9/34 , G06F9/345 , G06F9/3824 , G06F9/3891 , G06F9/462 , G06F9/54 , G06F9/544 , G06F15/163 , G06F15/7825
摘要: A network on a chip processor uses uniform addressing for both conventional memory and operand registers. The processor contains a large number of processing elements (e.g., 256). Each processing element has a number (e.g., 200) of operand registers to which it has direct, high-speed (e.g., single clock-cycle) access. Each of these operand registers is also assigned a global memory address, so other processing elements can read or write those operand registers as if they were located in main memory. Software that expects communication between processing elements to happen via memory can use memory-based reads/writes, but gain substantial speed by writing that data directly to the operand registers used for execution of instructions by the target processor.
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公开(公告)号:EP2243254B1
公开(公告)日:2018-07-18
申请号:EP07855748.5
申请日:2007-12-21
申请人: Intel Corporation
发明人: RUI, Kevin , ZHANG, Wenjie , DING, Johnathan , TANG, Alvin
CPC分类号: G06F9/45558 , G06F9/544 , G06F2009/45595 , H04L65/4084 , H04L67/104
摘要: Embodiments of apparatuses with a universal P2P service platform are disclosed herein. A unified infrastructure is built in such apparatuses and a unified P2P network may be established with such apparatuses. In various embodiments, such an apparatus comprises a P2P operating system (OS) virtual machine (VM) 202 and a client guest operating system (OS) virtual machine (VM) 204. There is a collection of P2P services in the P2P OS VM 202 and this VM 202 works as a peer node in the P2P network. There is a collection of API services in the client guest OS VM 204 and this VM 204 interacts with various P2P applications. The two VMs communicate with each other via a shared memory 216 and a virtual machine manager 214. In various embodiments, the apparatus further includes a security checker 318 located in the P2P OS VM 302. Other embodiments are also described.
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公开(公告)号:EP3204863A4
公开(公告)日:2018-07-11
申请号:EP14903767
申请日:2014-10-07
申请人: SYNOPSYS INC
发明人: ELIAS ANDREW ALEXANDER , THIBAULT JEAN-PIERRE , BOWLER NICK , LOUGHEED STEVEN , LEWIS MICHAEL JAMES
IPC分类号: G06F13/38 , G06F9/54 , G06F12/02 , G06F13/12 , H04N21/4363 , H04N21/4367 , H04N21/6334 , H04N21/835
CPC分类号: H04N21/835 , G06F9/54 , G06F9/544 , H04N21/43635 , H04N21/4367 , H04N21/6334
摘要: A system and method for communicating data between a first software and a second software located on first and second devices, respectively, has a hardware driver and memory associated with each device. Each communication of data from the first software to the second software allocates memory to manage data to be communicated from the first software to the second software, provides memory allocation information to the hardware driver associated with the first software, and transmits the data from the first hardware driver to the second hardware driver for delivery to the second software via the memory associated with the second software.
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公开(公告)号:EP2643961B1
公开(公告)日:2018-05-30
申请号:EP11799762.7
申请日:2011-11-21
申请人: Orange
发明人: GIRAUD, Jérôme , HELIOT, Mathieu
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