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16 条记录 (耗时 0.013 秒)

    A memory module utilizing partially defective memory chips
    1.
    发明公开
    A memory module utilizing partially defective memory chips 失效
    Speerthermodel unter Benutzung teilweiser Defektspeicherchips。

    公开(公告)号：EP0434901A2

    公开(公告)日：1991-07-03

    申请号：EP90115982.2

    申请日：1990-08-21

    申请人： International Business Machines Corporation

    发明人： Busch, Robert Edward ,  Ellis, Wayne Frederick ,  Redman, Theodore Milton ,  Thoma, Endre Philip

    IPC分类号： G06F11/20

    CPC分类号： G11C29/76

    摘要： A memory device which includes several partially defective memory chips and a control circuit (1) for receiving an address signal corresponding to a storage cell address of each of the partially defective memory chips, and for controlling, in response to the address signal, the partially defective memory chips such that only one thereof is enabled.
    The control circuit according to the invention can be implemented to control the chip driver circuit of a variety of different sizes of memory chips. For example, the control circuit can be implemented for controlling the chip driver circuit of a one-quarter size memory chip, a one-half size memory chip, a three-quarter size memory chip, or a full-size memory chip.

    摘要翻译： 一种包括若干部分缺陷的存储器芯片的存储器件和用于接收对应于每个部分缺陷存储器芯片的存储单元地址的地址信号的控制电路（1），并且用于响应于地址信号来控制部分 有缺陷的存储器芯片，使得其中只有一个被使能。 可以实现根据本发明的控制电路来控制各种不同大小的存储器芯片的芯片驱动器电路。 例如，控制电路可以被实现用于控制四分之一大小的存储器芯片，二分之一大小的存储器芯片，三分之四大小的存储器芯片或全尺寸存储器芯片的芯片驱动器电路。

    Memory system comprising dynamic memory cells
    2.
    发明公开
    Memory system comprising dynamic memory cells 失效
    具有动态存储器单元的存储器阵列。

    公开(公告)号：EP0055339A2

    公开(公告)日：1982-07-07

    申请号：EP81108127.2

    申请日：1981-10-09

    申请人： International Business Machines Corporation

    发明人： Thoma, Endre Philip

    IPC分类号： G11C11/24

    CPC分类号： G11C11/4094 ,  G11C11/409

    摘要： Memory system comprising dynamic memory cells, wherein each cell comprises a switchable cell device (10) and a capacitive node (12), wherein said switchable cell device [10) is connected to a bit line (14) to read the charge stored at said (12) node and to a first word line (16) to selectively switch said cell device (10) responsive to a first signal in said word line (16).
    Means are provided for rewriting the cell after reading without discharging the bit line to thereby improve cycle time. The cell includes an independently operated device (24) to access the capacitive storage node (12) to discharge the node of any charge thereon after the reading of a low or no charge bit on the capacitive storage node.

    Data output impedance control
    3.
    发明公开
    Data output impedance control 失效
    Steuerung von Datenausgangsimpedanz。

    公开(公告)号：EP0573816A2

    公开(公告)日：1993-12-15

    申请号：EP93108000.6

    申请日：1993-05-17

    申请人： International Business Machines Corporation

    发明人： Sartwell, Alfred Leonard ,  Thoma, Endre Philip

    IPC分类号： G11C29/00 ,  G01R31/28 ,  G06F11/26

    CPC分类号： G01R31/31701

    摘要： The present invention provides an apparatus and method for monitoring the functioning of a special operational mode on an integrated circuit module (20) without the need for a special or dedicated pin. By monitoring the data output pins (47) of the module operation in a special operational mode and premature interruption thereof, is detected. Delayed transition from a state of low impedance to a state of high impedance during the data output cycle is indicative of the special operational mode. The modules (20) which usually have tri-state devices (22) on their output lines (47) are provided with delay circuitry to delay the transition of the tri-state device (22), during the data output cycle, from a state of low impedance to a state of high impedance while the device remains in a special operating mode.

    摘要翻译： 本发明提供一种用于在集成电路模块（20）上监视特殊操作模式的功能的装置和方法，而不需要特殊或专用的引脚。 通过监视特殊操作模式下的模块操作的数据输出引脚（47）和其过早的中断来检测。 在数据输出周期期间从低阻抗状态到高阻抗状态的延迟转换表示特殊操作模式。 在其输出线（47）上通常具有三态装置（22）的模块（20）设置有延迟电路，以在数据输出周期期间延迟三态装置（22）从状态 的低阻抗处于高阻抗状态，而器件保持在特殊的工作模式。

    Metal-Oxide-Semiconductor Memory
    5.
    发明公开
    Metal-Oxide-Semiconductor Memory 失效
    MOS-斯派克。

    公开(公告)号：EP0291706A2

    公开(公告)日：1988-11-23

    申请号：EP88106204.6

    申请日：1988-04-19

    申请人： International Business Machines Corporation

    发明人： Busch, Robert Edward ,  Thoma, Endre Philip

    IPC分类号： G11C7/00 ,  G11C7/06 ,  G11C11/409

    CPC分类号： G11C7/18 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4097

    摘要： A dual sense amplifier construction with divided bit line isolation. A switch is disposed at approximately the midpoint of a bit line to divide the bit line into first and second bit line segments. When opened, the switch provides electrical isolation between the first and second bit line segments so that an accessed memory charge can be isolated from one-half of the capacitance associated with the bit line. Once the isolated memory charge is read and pre-amplified, the remaining bit line capacitance is no longer of concern. The switch is then closed to provide electrical connection between the first and second bit line segments, thereby allowing the completion of the amplification operation.

    摘要翻译： 具有分立位线隔离的双声道放大器结构。 开关设置在位线的大致中点处，以将位线分成第一位线段和第二位线段。 当打开时，开关提供第一和第二位线段之间的电隔离，使得访问的存储器电荷可以与与位线相关联的电容的一半隔离。 一旦分离的存储器电荷被读取并被预放大，剩余的位线电容就不再是关注的了。 然后关闭开关以在第一和第二位线段之间提供电连接，从而允许完成放大操作。

    Data output impedance control
    7.
    发明公开
    Data output impedance control 失效
    数据输出阻抗的控制。

    公开(公告)号：EP0573816A3

    公开(公告)日：1994-11-23

    申请号：EP93108000.6

    申请日：1993-05-17

    申请人： International Business Machines Corporation

    发明人： Sartwell, Alfred Leonard ,  Thoma, Endre Philip

    IPC分类号： G11C29/00 ,  G01R31/28 ,  G06F11/26

    CPC分类号： G01R31/31701

    摘要： The present invention provides an apparatus and method for monitoring the functioning of a special operational mode on an integrated circuit module (20) without the need for a special or dedicated pin. By monitoring the data output pins (47) of the module operation in a special operational mode and premature interruption thereof, is detected. Delayed transition from a state of low impedance to a state of high impedance during the data output cycle is indicative of the special operational mode. The modules (20) which usually have tri-state devices (22) on their output lines (47) are provided with delay circuitry to delay the transition of the tri-state device (22), during the data output cycle, from a state of low impedance to a state of high impedance while the device remains in a special operating mode.