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公开(公告)号：EP0511560A2
公开(公告)日：1992-11-04
申请号：EP92106611.4
申请日：1992-04-16
发明人： Abadeer, Wagdi William , El-Kareh, Badih , Ellis, Wayne Frederick , Galbi, Duane Elmer , Hiltebeitel, Nathan Rafael , Tonti, William Robert , Watts, Josef Samuel
CPC分类号： G11C29/785 , G11C17/14 , G11C17/16
摘要： A programmable storage element for redundancy-programming includes a programmable antifuse circuit which includes a plurality of first resistors (F1a, F1b, F1c) and a switching circuit (Q Fa , Q Fb , Q Fc , Q Fd ) for coupling the first resistors in series in response to a plurality of first control signals (Ta, Tb, Tc, Td) and for coupling the first resistors in parallel in response to a plurality of second control signals to permit programming of the first resistors, and a sensing circuit for determining whether or not the first resistors have been programmed. The state of the first resistors is determined by comparing a first voltage drop across the first resistors with a second voltage drop across a second resistor. Each of the first resistors is an unsilicided polysilicon conductor which has an irreversible resistance decrease when a predetermined threshold current is applied for a minimum period of time.
摘要翻译： 用于冗余编程的可编程存储元件包括可编程反熔丝电路，其包括多个第一电阻器（F1a，F1b，F1c）和用于响应于第一电阻器串联耦合第一电阻器的开关电路（QFa，QFb，QFc，QFd） 多个第一控制信号（Ta，Tb，Tc，Td），并且用于响应于多个第二控制信号并联耦合第一电阻器以允许编程第一电阻器;以及感测电路，用于确定是否 第一个电阻已编程。 第一电阻器的状态通过将第一电阻器两端的第一电压降与第二电阻器上的第二电压降进行比较来确定。 第一电阻器中的每一个是非极性多晶硅导体，当预定阈值电流施加最小时间时，其具有不可逆电阻降低。
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公开(公告)号：EP0434904A3
公开(公告)日：1992-05-13
申请号：EP90116851.8
申请日：1990-09-03
CPC分类号： G11C8/08 , G11C11/401 , G11C29/50 , G11C2029/5004
摘要： A signal margin testing system is provided for a memory having a word line voltage boosting circuit (42, C B ) which uses a test mode decode circuit (38) to selectively disable the word line boosting circuit (42, C B ) and then read out data from storage cells in the memory.
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3.发明公开Memory device with programmable self-refreshing and testing methods therefore 失效用于测试具有一个可编程的自刷新存储器的方法和装置。
公开(公告)号：EP0674320A1
公开(公告)日：1995-09-27
申请号：EP95480025.6
申请日：1995-03-21
IPC分类号： G11C29/00 , G11C11/406
CPC分类号： G11C11/406 , G11C29/02
摘要： A programmable self-timed refresh circuit for a semiconductor memory array and methods for programming the self-refresh rate and for non-invasively and deterministically testing the self-timed refresh circuit for establishing/verifying a refresh rate and a wait state interval for the self-refresh operation. The programmable refresh circuit includes a self-timed oscillator that outputs a clocking signal, and a programmable pattern generator that outputs a first signal pattern and a second signal pattern. The first signal pattern is fed to a counter circuit which also receives the clocking signal. The counter circuit outputs a signal pulse whenever the count driven by the clocking signal reaches a digital pattern representation corresponding to the first signal pattern generated by the programmable pattern generator. Refresh control logic is connected to receive the pulse signal and respond thereto by refreshing a portion of the memory array of the semiconductor memory device. The second signal pattern is employed by the refresh control logic to set the wait state interval for the self-refresh operation. Multiple methods for testing the programmable self-refresh circuit are also set forth.
摘要翻译： 可编程刷新电路包括自定时振荡器做输出时钟信号，和一个可编程图案发生器做输出的第一信号图案和第二信号图案。 第一信号图案被馈送到计数器电路，其因此接收该时钟信号，并输出每当由时钟信号驱动的计数达到的数字模式表示对应于100的信号脉冲。 到由可编程图案产生器产生的第一信号模式。 刷新控制逻辑被连接以接收所述脉冲信号并且通过刷新的半导体存储装置的存储器阵列的一部分对其进行响应。 第二信号图案由刷新控制逻辑用来设置用于自刷新操作等待状态的时间间隔。 所述的半导体装置从连接到它的控制系统接收行地址选通（RAS）信号和列地址选通（CAS）信号，并从之前的控制系统接收的信号的RAS转换信号发起自刷新包括CAS。
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公开(公告)号：EP0595748A1
公开(公告)日：1994-05-04
申请号：EP93480138.2
申请日：1993-09-21
发明人： Divakaruni, Sridhar , Ellis, Wayne Frederick , Kalter, Howard Leo , Dreibelbis, Jeffrey Harris , Furman, Anatol
IPC分类号： H03K17/22
CPC分类号： H03K17/223
摘要： A power up detection circuit is provided which includes a power supply terminal, an output terminal, an impedance device coupling the output terminal to the power supply terminal and a latch including a first inverter having a first device connected between the output terminal and a point of reference potential and a second device connected between the output terminal and the power supply terminal, the devices are designed so that subthreshold current passing through the first device is greater than the effective subthreshold current passing through the impedance device and the second device, and a second inverter including third and fourth devices which are designed so that a smaller subthreshold current passes through the third device than the subthreshold current passing through the fourth device. The power up circuit may further include a capacitor connected between the power supply terminal and gate electrodes of the first and second devices.
摘要翻译： 提供了一种上电检测电路，其包括电源端子，输出端子，将输出端子耦合到电源端子的阻抗装置和包括第一逆变器的锁存器，第一逆变器具有连接在输出端子和点 参考电位和连接在输出端子和电源端子之间的第二器件，器件被设计成使得通过第一器件的亚阈值电流大于通过阻抗器件和第二器件的有效亚阈值电流， 逆变器包括第三和第四器件，其被设计为使得比通过第四器件的亚阈值电流更小的亚阈值电流通过第三器件。 上电电路还可以包括连接在第一和第二器件的电源端子和栅电极之间的电容器。
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5.发明公开A memory module utilizing partially defective memory chips 失效Speerthermodel unter Benutzung teilweiser Defektspeicherchips。
公开(公告)号：EP0434901A2
公开(公告)日：1991-07-03
申请号：EP90115982.2
申请日：1990-08-21
IPC分类号： G06F11/20
CPC分类号： G11C29/76
摘要： A memory device which includes several partially defective memory chips and a control circuit (1) for receiving an address signal corresponding to a storage cell address of each of the partially defective memory chips, and for controlling, in response to the address signal, the partially defective memory chips such that only one thereof is enabled.
The control circuit according to the invention can be implemented to control the chip driver circuit of a variety of different sizes of memory chips. For example, the control circuit can be implemented for controlling the chip driver circuit of a one-quarter size memory chip, a one-half size memory chip, a three-quarter size memory chip, or a full-size memory chip.摘要翻译： 一种包括若干部分缺陷的存储器芯片的存储器件和用于接收对应于每个部分缺陷存储器芯片的存储单元地址的地址信号的控制电路（1），并且用于响应于地址信号来控制部分 有缺陷的存储器芯片，使得其中只有一个被使能。 可以实现根据本发明的控制电路来控制各种不同大小的存储器芯片的芯片驱动器电路。 例如，控制电路可以被实现用于控制四分之一大小的存储器芯片，二分之一大小的存储器芯片，三分之四大小的存储器芯片或全尺寸存储器芯片的芯片驱动器电路。
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公开(公告)号：EP0434901A3
公开(公告)日：1992-10-14
申请号：EP90115982.2
申请日：1990-08-21
IPC分类号： G06F11/20
CPC分类号： G11C29/76
摘要： A memory device which includes several partially defective memory chips and a control circuit (1) for receiving an address signal corresponding to a storage cell address of each of the partially defective memory chips, and for controlling, in response to the address signal, the partially defective memory chips such that only one thereof is enabled. The control circuit according to the invention can be implemented to control the chip driver circuit of a variety of different sizes of memory chips. For example, the control circuit can be implemented for controlling the chip driver circuit of a one-quarter size memory chip, a one-half size memory chip, a three-quarter size memory chip, or a full-size memory chip.
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公开(公告)号：EP0434904A2
公开(公告)日：1991-07-03
申请号：EP90116851.8
申请日：1990-09-03
CPC分类号： G11C8/08 , G11C11/401 , G11C29/50 , G11C2029/5004
摘要： A signal margin testing system is provided for a memory having a word line voltage boosting circuit (42, C B ) which uses a test mode decode circuit (38) to selectively disable the word line boosting circuit (42, C B ) and then read out data from storage cells in the memory.
摘要翻译： 为具有字线升压电路（42，CB）的存储器提供信号容限测试系统，该字线电压升压电路使用测试模式解码电路（38）选择性地禁用字线升压电路（42，CB），然后读出数据 从存储器中的存储单元。
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公开(公告)号：EP0130273B1
公开(公告)日：1989-05-10
申请号：EP84101728.8
申请日：1984-02-20
IPC分类号： H03K19/017 , H03K5/02
CPC分类号： H03K19/01721 , H03K19/01714
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公开(公告)号：EP0130273A3
公开(公告)日：1986-11-12
申请号：EP84101728
申请日：1984-02-20
IPC分类号： H03K19/017 , H03K05/02
CPC分类号： H03K19/01721 , H03K19/01714
摘要： A driver or pull up circuit is provided which includes a pull up transistor (T5) of a given conductivity type and a precharged bootstrap capacitor (C B ) which discharges fully through a second transistor (T3) having a conductivity type opposite to that of the pull up transistor to the control gate or electrode of the pull up transistor. A further transistor (T1) may be used to initiate discharge by providing power supply voltage to the control gate of the pull up transistor.
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10.发明授权Memory device with programmable self-refreshing and testing methods therefore 失效用于测试具有一个可编程的自刷新的存储器的方法和装置
公开(公告)号：EP0674320B1
公开(公告)日：2000-05-24
申请号：EP95480025.6
申请日：1995-03-21
IPC分类号： G11C29/00 , G11C11/406
CPC分类号： G11C11/406 , G11C29/02
摘要： The programmable refresh circuit includes a self-timed oscillator that outputs a clocking signal, and a programmable pattern generator that outputs a first signal pattern and a second signal pattern. The first signal pattern is fed to a counter circuit which also receives the clocking signal and outputs a signal pulse whenever the count driven by the clocking signal reaches a digital pattern representation corresp. to the first signal pattern generated by the programmable pattern generator. Refresh control logic is connected to receive the pulse signal and respond to it by refreshing a portion of the memory array of the semiconductor memory device. The second signal pattern is employed by the refresh control logic to set the wait state interval for the self-refresh operation. The semiconductor device receives row address strobe (RAS) signal and column address strobe (CAS) signal from the control system connected to it, and signal initiating self-refresh comprises CAS before RAS transition of signals received from control systems.
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