Processor
    1.
    发明公开
    Processor 有权
    处理器

    公开(公告)号:EP0901061A3

    公开(公告)日:2000-02-02

    申请号:EP98116615.0

    申请日:1998-09-02

    IPC分类号: G06F1/10

    CPC分类号: G06F13/1689 G06F1/10

    摘要: An operation controller, an operation unit and a memory are provided. The operation controller always receives a non-gated clock signal from a clock controller. When an operation initiating signal and a parameter signal indicating resources to be used in the operation unit are generated by a microcontroller, the operation controller asserts a request signal. In response to the request signal, respective gated clock signals are supplied from the clock controller to the operation unit and to the memory. The operation controller determines whether or not a status signal supplied from the operation unit satisfies a predetermined end condition. If the signal satisfies the end condition, the operation controller negates the request signal. As a result, the supply of the clock signals to the operation unit and to the memory is stopped.

    Processor
    3.
    发明公开
    Processor 有权
    Prozessor

    公开(公告)号:EP0901061A2

    公开(公告)日:1999-03-10

    申请号:EP98116615.0

    申请日:1998-09-02

    IPC分类号: G06F1/10

    CPC分类号: G06F13/1689 G06F1/10

    摘要: An operation controller, an operation unit and a memory are provided. The operation controller always receives a non-gated clock signal from a clock controller. When an operation initiating signal and a parameter signal indicating resources to be used in the operation unit are generated by a microcontroller, the operation controller asserts a request signal. In response to the request signal, respective gated clock signals are supplied from the clock controller to the operation unit and to the memory. The operation controller determines whether or not a status signal supplied from the operation unit satisfies a predetermined end condition. If the signal satisfies the end condition, the operation controller negates the request signal. As a result, the supply of the clock signals to the operation unit and to the memory is stopped.

    摘要翻译: 提供操作控制器,操作单元和存储器。 操作控制器总是从时钟控制器接收非门控时钟信号。 当由微控制器产生指示要在操作单元中使用的资源的操作启动信号和参数信号时,操作控制器断言请求信号。 响应于请求信号,相应的门控时钟信号从时钟控制器提供给操作单元和存储器。 操作控制器确定从操作单元提供的状态信号是否满足预定的结束条件。 如果信号满足结束条件,则操作控制器取消请求信号。 结果,停止向操作单元和存储器提供时钟信号。