公开(公告)号：EP0213971A3

公开(公告)日：1988-12-14

申请号：EP86401085

申请日：1986-05-22

申请人： Monolithic Memories, Inc.

发明人： Birkner, John ,  Chua, Hua Thye ,  Chan, Andrew K.L. ,  Chan, Albert

IPC分类号： H03K19/177

CPC分类号： H03K19/17708 ,  H03K19/17712

摘要： A programmable logic array (100) includes a set of input terms which are programmably coupled to a first set of AND gates (102-1 through 102-66). The output signals from the first set of AND gates are programmably elec­trically connected to a second set of AND gates (104-1 through 104-66). The second set of programmable AND gates enhances flexibility of design and permits product terms with a larger number of factors to be generated. The output leads from the second set of AND gates are programmably electrically coupled to a first set of OR gates (106-1 through 106-22) which in turn are program­mably electrically coupled to a second array of OR gate logic (108-1 through 108-10). This also permits greater design flexibility. The output terms from the second set of OR gate logic can then be used to generate the output signals from the programmable logic array (100). In addition, a bus (110) is programmably electrically coup­led to each of the output signals from the second OR logic array and the output pins (O₁ through O₁₀) of the PLA. Because of this, different output terms can be routed to different output pins thus permitting the designer to select his pin out independently of the availability of gate within specific parts of the array.