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    DEPOPULATED PROGRAMMABLE LOGIC ARRAY
    1.
    发明公开
    DEPOPULATED PROGRAMMABLE LOGIC ARRAY 审中-公开
    简化可编程逻辑阵列

    公开(公告)号：EP1354405A2

    公开(公告)日：2003-10-22

    申请号：EP01968526.2

    申请日：2001-09-06

    申请人： Lightspeed Semiconductor Corporation

    发明人： OSANN, Robert ,  HALLINAN, Patrick ,  LEE, Jung ,  MUKUND, Shridhar

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17708

    摘要： A programmable logic array (PLA) in accordance with the invention achieves a maximum amount of depopulation of programmable connections while sill implementing a logic function and maintaining flexibility for future reprogramming. In addition, a PLA in accordance with the invention can be built so that no matter what functionality is programmed, performance characteristics for the device are maintained. Further, a PLA in accordance with the invention does not require a regular array structure.

    COMBINED PROGRAMMABLE LOGIC ARRAY AND ARRAY LOGIC
    2.
    发明授权
    COMBINED PROGRAMMABLE LOGIC ARRAY AND ARRAY LOGIC 失效
    合并，解放军PAL电路

    公开(公告)号：EP0733285B1

    公开(公告)日：1999-11-10

    申请号：EP95927941.5

    申请日：1995-08-30

    申请人： Koninklijke Philips Electronics N.V.

    发明人： CLINE, Ronald, Lee

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17708

    摘要： A PLD comprises a programmable first AND array whose inputs are selectively connectable to input lines and whose outputs are selectively connectable to a programmable second OR array. The PLD further comprises a programmable third AND array whose inputs are selectively connectable to the input lines, and whose outputs are fixedly connected to inputs of a fixed fourth OR array. The outputs from the second OR array are also connected in a fixed manner to the fourth OR array. This arrangement overcomes some of the weaknesses in both the conventional PAL and PLA architectures while retaining most of their strengths.

    PROGRAMMABLE LOGIC EXPANDER
    3.
    发明授权
    PROGRAMMABLE LOGIC EXPANDER 失效
    逻辑扩展可编程器件

    公开(公告)号：EP0472650B1

    公开(公告)日：1997-03-19

    申请号：EP90908864.3

    申请日：1990-05-09

    申请人： Xilinx, Inc.

    发明人： KAPLINSKY, Cecil, H.

    IPC分类号： H03K19/177 ,  H03K19/173

    CPC分类号： H03K19/17708

    摘要： A programmable logic device that provides an AND gate array connected to an OR gate array connected to a third logic level, a logic expander module (121, 123). The module provides programmable selection of any of 16 one- and two-variable logic functions or any of 256 one-, two- and three-variable logic functions. In one embodiment (11, 61), the invention uses logic function gates such as AND, OR, XOR and inverter gates to form the logic functions. In a second embodiment (91) and a third embodiment, a look-up table and an array of pass transistors, respectively, are used to form the logic functions.

    Josephson logic gate having a plurality of input ports and a Josephson logic circuit that uses such a Josephson logic gate
    8.
    发明公开
    Josephson logic gate having a plurality of input ports and a Josephson logic circuit that uses such a Josephson logic gate 失效
    具有多个输入端口和与该门电路约瑟夫森的约瑟夫森栅极。

    公开(公告)号：EP0506345A2

    公开(公告)日：1992-09-30

    申请号：EP92302541.5

    申请日：1992-03-25

    申请人： FUJITSU LIMITED

    发明人： Suzuki, Hideo, c/o Fujitsu Limited

    IPC分类号： H03K19/195

    CPC分类号： H03K19/17708 ,  H03K19/1952 ,  H03M7/003

    摘要： A multiple-input Josephson AND gate having a plurality of input ports (A₁ - A₄) comprises a plurality of Josephson logic gate elements (11 - 14) provided in number corresponding to a number of said input ports and cascaded with each other from a first stage to a final stage, each of the Josephson logic gate elements of said first through final stages including: a superconducting quantum interferometer (S₁ - S₄) for producing an output signal in response to a transition from a superconducting state to a finite voltage state, an input line connected to a corresponding input port for carrying thereon an input current, the input line being coupled magnetically to the superconducting quantum interferometer for transferring the input current to said superconducting quantum interferometer; and a biasing part (J₂ - J₄) for supplying a bias current to the superconducting quantum interferometer with a level such that the superconducting quantum interferometer causes the transition to the finite voltage stage in response to the input current supplied to the input line, wherein each of the biasing part of the second through final stages are supplied with the output signal of the superconducting quantum interferometer of the previous stage as a trigger signal and produces the bias current in response to the trigger signal.

    摘要翻译： 具有输入端口（A1 - A4）的多个A多输入约瑟夫森AND门包括约瑟夫逊逻辑门元件的多个（11 - 14）从第一对应于多个所述输入端口号设置并且彼此级联 阶段到最后阶段，每个第一至包含最后阶段。所述的约瑟夫逊逻辑栅极元件：一个超导量子干涉仪（S1 - S4），用于响应于输出信号产生于从超导状态转变到有限电压状态， 上连接到对应的输入端口，用于在其上携带到输入电流输入线时，输入线被磁性地耦合到用于传递环的输入电流到所述超导量子干涉仪中的超导量子干涉仪; 和偏置部（J2 - J4），用于提供偏置电流用的电平的超导量子干涉仪检查没有超导量子干涉仪使过渡到有限电压级响应于提供给输入线的输入电流，worin每个 通过最后阶段的第二偏压部分被提供与前级作为触发信号的超导量子干涉仪的输出信号，并产生响应于该触发信号的偏置电流。

    Programmable logic array using emitter-coupled logic and input buffer
    9.
    发明公开
    Programmable logic array using emitter-coupled logic and input buffer 失效
    Programmierbares logisches Feld unter Verwendung von ECL-Logik und -Eangangspuffern。

    公开(公告)号：EP0462682A2

    公开(公告)日：1991-12-27

    申请号：EP91202451.0

    申请日：1986-03-19

    申请人： ADVANCED MICRO DEVICES, INC.

    发明人： Hoberman, Barry A. ,  Moss, William E.

    IPC分类号： H03K19/177

    CPC分类号： H03K19/0016 ,  H03K19/01806 ,  H03K19/17708

    摘要： A novel ECL Programmable Logic Array (PLA) is provided which operates as an ECL PLA, having ECL voltage level compatible input and output leads, thereby providing a high-speed PLA. A unique programming means is provided which allows the ECL PLA to be programmed using TTL-compatible programming voltage levels, such as are provided by common and inexpensive prior art TTL PLA programmers. In another embodiment higher speed is achieved by the design of each sense amplifier using emitter function logic such that the sense transistor and load functions a cascode amplifier. In another embodiment a lower power PLA device is achieved by utilizing a switched current source pull down means for pulling down the rows of the PLA array. In another embodiment low power and user convenience is achieved by allowing each pair of output terminals to share a predefined set of product terms. In another embodiment of this invention, each output terminal is capable of having its output polarity programmed, in order to provide either a desired product term, or the inverse of that product term.

    摘要翻译： 提供了一种新型的ECL可编程逻辑阵列（PLA），其作为ECL PLA操作，具有ECL电压电平兼容的输入和输出引线，从而提供高速PLA。 提供了一种独特的编程手段，使得ECL PLA可以使用TTL兼容的编程电压电平进行编程，例如由普通和便宜的现有技术的TTL PLA编程器提供。 在另一个实施例中，通过使用发射器功能逻辑的每个读出放大器的设计实现更高的速度，使得感测晶体管和负载对共源共栅放大器起作用。 在另一个实施例中，通过利用用于下拉PLA阵列的行的开关电流源下拉装置来实现较低功率的PLA装置。 在另一实施例中，通过允许每对输出终端共享预定义的一组产品项来实现低功率和用户便利性。 在本发明的另一个实施例中，每个输出端能够使其输出极性被编程，以便提供期望的乘积项或该乘积项的倒数。

    Low power consumption programmable logic array (PLA) and data processing system incorporating the PLA
    10.
    发明公开
    Low power consumption programmable logic array (PLA) and data processing system incorporating the PLA 失效
    可编程逻辑阵列（PLA），低功耗和数据处理系统与此PLA。

    公开(公告)号：EP0458362A2

    公开(公告)日：1991-11-27

    申请号：EP91108485.3

    申请日：1991-05-24

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Horie, Atsushi ,  Utsumi, Tohru

    IPC分类号： H03K19/177 ,  H03K19/00 ,  G06F9/22

    CPC分类号： H03K19/0016 ,  H03K19/17708 ,  H03K19/1772

    摘要： Disclosed is a programmable logic array (PLA), comprising an AND plane comprising a plurality of input lines (10) and a plurality of product term lines (11) crossing the input lines (10), an OR plane comprising the product term lines (11) and a plurality of output lines (12) crossing the product term lines (11), a power source VDD providing an electrical power to the AND and OR planes, and control line for controlling the supply of the electric power to the AND and OR planes, wherein the electrical power from the power source VDD is provided to the PLA when a signal indicating the use of the PLA is provided to the control line, and the supply of the electrical power from the power source VDD to the PLA is stopped on receipt of a signal designating that the PLA is in the unused state. In addition, various data processing systems incorporating the PLA are disclosed.

    摘要翻译： 本发明提供一种可编程逻辑阵列（PLA），包含与平面包括输入线交叉的输入线有多个（10）和的乘积项线有多个（11）（10），计划或包含积项线（ 11）和输出线（交叉的乘积项线（11），电源VDD到AND和OR平面提供电力的，和控制线，用于控制电功率的给和提供多个12）和 或平面，worin从当指示使用PLA的信号被提供到控制线VDD被提供给PLA的电源，并且所述电功率从电源VDD到PLA供给的电功率被停止 在收到信号指定的那样，解放军是未使用状态。 此外，结合中国人民解放军各种数据处理系统是游离缺失盘。