公开(公告)号：EP1913692B1

公开(公告)日：2010-04-28

申请号：EP06780213.2

申请日：2006-07-26

申请人： NXP B.V.

发明人： FIFIELD, Robert, c/o Philips Intellectual Property & Standards

IPC分类号： H03H17/02

CPC分类号： H03H17/0227 ,  H03H17/0225

公开(公告)号：EP1913692A2

公开(公告)日：2008-04-23

申请号：EP06780213.2

申请日：2006-07-26

申请人： NXP B.V.

发明人： FIFIELD, Robert, c/o Philips Intellectual Property & Standards

IPC分类号： H03H17/02

CPC分类号： H03H17/0227 ,  H03H17/0225

摘要： A FIR filter (20) has a delay line comprising four delay elements (21a, 21 b, 21c, 21 d) for delaying a signal received at a filter input (22) and four multipliers (24a, 24b, 24c, 24d) for multiplying the delayed signals by respective partial filter coefficients a, b, c, d. The delay elements (21a, 21 b, 21c, 21 d) and multipliers (24a, 24b, 24c, 24d) are connected alternately in series. Four taps (23a, 23b, 23c, 23d) extract the signal from the delay line immediately after each of the delay elements (21a, 21 b, 21c, 21 d) and output the delayed, multiplied signals to an adder (25) for adding the delayed, multiplied signals to generate a filter output (26). The partial filter coefficients a, b, c, d effectively combine to implement filter coefficients A, B, C, D for the taps (23a, 23b, 23c, 23d), e.g. with A = a, B = a*b, C = a*b*c and D = a*b*c*d. Use of such partial filter coefficients a, b, c, d can significantly reduce the number of operations required for multiplication in the FIR filter (20) in comparison to the prior art.