公开(公告)号：EP0838772A2

公开(公告)日：1998-04-29

申请号：EP97117782.9

申请日：1997-10-14

申请人： QUICKTURN DESIGN SYSTEMS, INC.

发明人： Sample, Stephen P. ,  Bershteyn, Mikhail

IPC分类号： G06F17/50

CPC分类号： G06F17/5027

摘要： A method and apparatus for combining emulation and simulation of a logic design. The method and apparatus can be used with a logic design that includes gate-level descriptions, behavioral representations, structural representations, or a combination thereof. The emulation and simulation portions are combined in a manner that minimizes the time for transferring data between the two portions. Simulation is performed by one or more microprocessors while emulation is performed in reconfigurable hardware such as field programmable gate arrays. When multiple microprocessors are employed, independent portions of the logic design are selected to be executed on the multiple synchronized microprocessors. Reconfigurable hardware also performs event detecting and scheduling operations to aid the simulation, and to reduce processing time.

摘要翻译： 一种用于组合逻辑设计的仿真和模拟方法和装置。 该方法和装置可以与逻辑设计中使用没有包括门级描述，行为的表示，结构表示，或它们的组合。 仿真和模拟部分以这样的方式被组合做最小化在两个部分之间传递环数据的时间。 如现场可编程门阵列：模拟由一个或多个微处理器，而仿真执行在重新配置的硬件来执行。 当多个微处理器采用，被选择的逻辑设计的独立部分上的所述多个同步的微处理器执行。 因此，可重构硬件执行事件检测和调度操作，以帮助仿真，并减少处理时间。

公开(公告)号：EP0838772A3

公开(公告)日：1998-05-13

申请号：EP97117782.9

申请日：1997-10-14

申请人： QUICKTURN DESIGN SYSTEMS, INC.

发明人： Sample, Stephen P. ,  Bershteyn, Mikhail

IPC分类号： G06F17/50

CPC分类号： G06F17/5027

摘要： A method and apparatus for combining emulation and simulation of a logic design. The method and apparatus can be used with a logic design that includes gate-level descriptions, behavioral representations, structural representations, or a combination thereof. The emulation and simulation portions are combined in a manner that minimizes the time for transferring data between the two portions. Simulation is performed by one or more microprocessors while emulation is performed in reconfigurable hardware such as field programmable gate arrays. When multiple microprocessors are employed, independent portions of the logic design are selected to be executed on the multiple synchronized microprocessors. Reconfigurable hardware also performs event detecting and scheduling operations to aid the simulation, and to reduce processing time.

摘要翻译： 一种用于组合逻辑设计的仿真和仿真的方法和设备。 该方法和装置可以与包括门级描述，行为表示，结构表示或其组合的逻辑设计一起使用。 仿真部分和仿真部分以最小化两部分之间传输数据的时间的方式组合。 仿真由一个或多个微处理器执行，而仿真在可重新配置的硬件（如现场可编程门阵列）中执行。 当采用多个微处理器时，逻辑设计的独立部分被选择为在多个同步微处理器上执行。 可重新配置的硬件还执行事件检测和调度操作以帮助模拟，并减少处理时间。