公开(公告)号：EP0838772A2

公开(公告)日：1998-04-29

申请号：EP97117782.9

申请日：1997-10-14

申请人： QUICKTURN DESIGN SYSTEMS, INC.

发明人： Sample, Stephen P. ,  Bershteyn, Mikhail

IPC分类号： G06F17/50

CPC分类号： G06F17/5027

摘要： A method and apparatus for combining emulation and simulation of a logic design. The method and apparatus can be used with a logic design that includes gate-level descriptions, behavioral representations, structural representations, or a combination thereof. The emulation and simulation portions are combined in a manner that minimizes the time for transferring data between the two portions. Simulation is performed by one or more microprocessors while emulation is performed in reconfigurable hardware such as field programmable gate arrays. When multiple microprocessors are employed, independent portions of the logic design are selected to be executed on the multiple synchronized microprocessors. Reconfigurable hardware also performs event detecting and scheduling operations to aid the simulation, and to reduce processing time.

摘要翻译： 一种用于组合逻辑设计的仿真和模拟方法和装置。 该方法和装置可以与逻辑设计中使用没有包括门级描述，行为的表示，结构表示，或它们的组合。 仿真和模拟部分以这样的方式被组合做最小化在两个部分之间传递环数据的时间。 如现场可编程门阵列：模拟由一个或多个微处理器，而仿真执行在重新配置的硬件来执行。 当多个微处理器采用，被选择的逻辑设计的独立部分上的所述多个同步的微处理器执行。 因此，可重构硬件执行事件检测和调度操作，以帮助仿真，并减少处理时间。

公开(公告)号：EP0838772A3

公开(公告)日：1998-05-13

申请号：EP97117782.9

申请日：1997-10-14

申请人： QUICKTURN DESIGN SYSTEMS, INC.

发明人： Sample, Stephen P. ,  Bershteyn, Mikhail

IPC分类号： G06F17/50

CPC分类号： G06F17/5027

摘要： A method and apparatus for combining emulation and simulation of a logic design. The method and apparatus can be used with a logic design that includes gate-level descriptions, behavioral representations, structural representations, or a combination thereof. The emulation and simulation portions are combined in a manner that minimizes the time for transferring data between the two portions. Simulation is performed by one or more microprocessors while emulation is performed in reconfigurable hardware such as field programmable gate arrays. When multiple microprocessors are employed, independent portions of the logic design are selected to be executed on the multiple synchronized microprocessors. Reconfigurable hardware also performs event detecting and scheduling operations to aid the simulation, and to reduce processing time.

摘要翻译： 一种用于组合逻辑设计的仿真和仿真的方法和设备。 该方法和装置可以与包括门级描述，行为表示，结构表示或其组合的逻辑设计一起使用。 仿真部分和仿真部分以最小化两部分之间传输数据的时间的方式组合。 仿真由一个或多个微处理器执行，而仿真在可重新配置的硬件（如现场可编程门阵列）中执行。 当采用多个微处理器时，逻辑设计的独立部分被选择为在多个同步微处理器上执行。 可重新配置的硬件还执行事件检测和调度操作以帮助模拟，并减少处理时间。

公开(公告)号：EP0919938A3

公开(公告)日：2002-04-17

申请号：EP98120863.0

申请日：1998-11-03

申请人： Quickturn Design Systems, Inc

发明人： Sample, Stephen P. ,  Butts, Michael R.

IPC分类号： G06F17/50 ,  H03K19/177

CPC分类号： H03K19/17736 ,  G06F15/7867 ,  G06F17/5027

摘要： A logic chip useful for emulation and prototyping of integrated circuits. The logic chip comprises a plurality of logic elements, which is divided into a plurality of subsets of logic elements. The logic chip further comprises a plurality of first level interconnects. The plurality of first level interconnects interconnect one of the plurality of subsets of logic elements, thereby forming a plurality of first level logical units. The plurality of first level logical units is divided into a plurality of subsets of first level logical units. The logic chip also comprises a plurality of second level interconnects. The second level interconnects interconnect one of the plurality of subsets of first level logic units, thereby forming a plurality of second level logic units. The logic chip also comprises a third level interconnect. The third level interconnect interconnects the plurality of second level logic units, thereby forming a third level logic

公开(公告)号：EP0919938A2

公开(公告)日：1999-06-02

申请号：EP98120863.0

申请日：1998-11-03

申请人： Quickturn Design Systems, Inc

发明人： Sample, Stephen P. ,  Butts, Michael R.

IPC分类号： G06F17/50

CPC分类号： H03K19/17736 ,  G06F15/7867 ,  G06F17/5027

摘要： A logic chip useful for emulation and prototyping of integrated circuits. The logic chip comprises a plurality of logic elements, which is divided into a plurality of subsets of logic elements. The logic chip further comprises a plurality of first level interconnects. The plurality of first level interconnects interconnect one of the plurality of subsets of logic elements, thereby forming a plurality of first level logical units. The plurality of first level logical units is divided into a plurality of subsets of first level logical units. The logic chip also comprises a plurality of second level interconnects. The second level interconnects interconnect one of the plurality of subsets of first level logic units, thereby forming a plurality of second level logic units. The logic chip also comprises a third level interconnect. The third level interconnect interconnects the plurality of second level logic units, thereby forming a third level logic

摘要翻译： 用于集成电路仿真和原型设计的逻辑芯片。 逻辑芯片包括多个逻辑元件，其被分成多个逻辑元件子集。 逻辑芯片还包括多个第一级互连。 多个第一级互连互连多个逻辑元件子集中的一个，从而形成多个第一级逻辑单元。 多个第一级逻辑单元被分成多个第一级逻辑单元子集。 逻辑芯片还包括多个第二级互连。 第二级互连将第一级逻辑单元的多个子集之一互连，由此形成多个第二级逻辑单元。 逻辑芯片还包括第三级互连。 第三级互连将多个第二级逻辑单元互连，从而形成第三级逻辑“IMAGE”

公开(公告)号：EP0574133B1

公开(公告)日：1999-12-01

申请号：EP93303580.0

申请日：1993-05-10

申请人： QUICKTURN DESIGN SYSTEMS, INC.

发明人： Sample, Stephen P. ,  Goode, Terry Lee

IPC分类号： H05K7/14 ,  H05K1/00 ,  H05K1/14

CPC分类号： H05K7/1445 ,  H05K1/14 ,  H05K2201/044

公开(公告)号：EP0574133A3

公开(公告)日：1995-09-20

申请号：EP93303580.0

申请日：1993-05-10

申请人： QUICKTURN DESIGN SYSTEMS, INC.

发明人： Sample, Stephen P. ,  Goode, Terry Lee

IPC分类号： H05K7/14 ,  H05K1/00 ,  G06F15/60 ,  H05K1/14

CPC分类号： H05K7/1445 ,  H05K1/14 ,  H05K2201/044

摘要： A physical interconnection architecture for making connections between a plurality of first printed-circuit boards and a plurality of second printed-circuit boards includes a midplane printed-circuit board having a plurality of first connectors oriented in a first direction mounted on a first face thereof for making connections to the first printed-circuit boards. Each first connector includes a plurality of rows of connection pins on a first face thereof for making electrical contact with the midplane printed-circuit board and a plurality of rows of connection pins on a second opposing face thereof for making electrical contact with conductors of a mating first printed-circuit board connector mounted on a printed-circuit board to be connected to the midplane printed-circuit board on its first face. A plurality of second connectors are mounted on a second face of the midplane printed-circuit board and are oriented in a second direction orthogonal to the first connectors. The second high-density printed-circuit-board connectors are used to make connections to mating connectors for printed-circuit boards to be connected to the midplane printed-circuit board on its second face. Each second connector includes a plurality of rows of connection pins on a first face thereof for making electrical contact with the midplane printed-circuit board and a plurality of rows of connection pins on a second opposing face thereof for making electrical contact with conductors of a mating second printed-circuit board connector mounted on a printed-circuit board to be connected to the midplane printed-circuit board on its first face. The row and column spacing of the connection pins of both the first and second connectors are equal. The connectors are positioned such that the connection pins in the region of intersection of the first and second connectors are double-ended connection pins common to both the first and second connectors. The remaining connection pins of the first and second connectors are single-ended connection pins which are connected to the single-ended connection pins of the second connectors by conductive traces on the midplane printed-circuit board.

公开(公告)号：EP0574133A2

公开(公告)日：1993-12-15

申请号：EP93303580.0

申请日：1993-05-10

申请人： QUICKTURN DESIGN SYSTEMS, INC.

发明人： Sample, Stephen P. ,  Goode, Terry Lee

IPC分类号： H05K7/14 ,  H05K1/00 ,  G06F15/60 ,  H05K1/14

CPC分类号： H05K7/1445 ,  H05K1/14 ,  H05K2201/044

摘要： A physical interconnection architecture for making connections between a plurality of first printed-circuit boards and a plurality of second printed-circuit boards includes a midplane printed-circuit board having a plurality of first connectors oriented in a first direction mounted on a first face thereof for making connections to the first printed-circuit boards. Each first connector includes a plurality of rows of connection pins on a first face thereof for making electrical contact with the midplane printed-circuit board and a plurality of rows of connection pins on a second opposing face thereof for making electrical contact with conductors of a mating first printed-circuit board connector mounted on a printed-circuit board to be connected to the midplane printed-circuit board on its first face. A plurality of second connectors are mounted on a second face of the midplane printed-circuit board and are oriented in a second direction orthogonal to the first connectors. The second high-density printed-circuit-board connectors are used to make connections to mating connectors for printed-circuit boards to be connected to the midplane printed-circuit board on its second face. Each second connector includes a plurality of rows of connection pins on a first face thereof for making electrical contact with the midplane printed-circuit board and a plurality of rows of connection pins on a second opposing face thereof for making electrical contact with conductors of a mating second printed-circuit board connector mounted on a printed-circuit board to be connected to the midplane printed-circuit board on its first face. The row and column spacing of the connection pins of both the first and second connectors are equal. The connectors are positioned such that the connection pins in the region of intersection of the first and second connectors are double-ended connection pins common to both the first and second connectors. The remaining connection pins of the first and second connectors are single-ended connection pins which are connected to the single-ended connection pins of the second connectors by conductive traces on the midplane printed-circuit board.

摘要翻译： 用于第一印刷电路板的多个部分并加以的第二印刷电路板之间的多个进行连接的物理互连体系结构包括具有安装在第一面，其用于沿第一方向定向的第一连接器的多个A平面的印刷电路板 使得到所述第一印刷电路板的连接。 每个第一连接器包括在第一面上的连接销行中的多个，其用于使上的第二相对面与中平面印刷电路板的电接触和连接销行中的多个，其用于使电接触配合的导体 安装在印刷电路板第一印刷电路板连接器被连接到中平面的印刷电路板在其第一面上。 的第二连接器的多个被安装在中平面的印刷电路板的第二面，并在第二方向正交于所述第一连接器被取向。 所述第二高密度印刷电路板连接器被用来对配合连接器的连接于印刷电路板被连接到中平面的印刷电路板在其第二面上。 每个第二连接器包括在第一面上的连接销行中的多个，其用于使上的第二相对面与中平面印刷电路板的电接触和连接销行中的多个，其用于使电接触配合的导体 安装在印刷电路板的第二印刷电路板连接器被连接到中平面的印刷电路板在其第一面上。 这两个第一和第二连接器的连接销的行和列的间隔是相等的。 连接器正在寻求定位的确在第一和第二连接器的交叉区域中的连接销两者共同的第一和第二连接器的双端连接销。 所述第一和第二连接器的剩余的连接引脚其通过在中平面的印刷电路板的导电迹线连接到所述第二连接器的单端连接管脚的单端连接的引脚。