公开(公告)号：EP1911160A1

公开(公告)日：2008-04-16

申请号：EP06732476.4

申请日：2006-04-24

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： KOYAMA, Jun SEMICONDUCTOR ENERGY LABORATORY COLTD ,  OSADA, Takeshi c/o Semiconductor Energy Lab.

IPC分类号： H03L7/099 ,  H03K3/354

CPC分类号： H03L7/0995 ,  H03K3/014 ,  H03K3/0315 ,  H03L7/085 ,  H03L7/099

摘要： A PLL circuit includes a phase detector, a loop filter (LF), a voltage-controlled oscillator (VCO), and a frequency divider. The phase detector compares a phase of a signal Fs which is input from outside with a phase of a signal Fo/N which is input from the frequency divider. The loop filter generates a signal Vin by removing alternating current components from a signal input from the phase detector. The voltage-controlled oscillator outputs a signal Fo based on the signal Vin input from the loop filter. The frequency divider converts the signal Fo output from the voltage-controlled oscillator into Fo/N (frequency division by N), and outputs it to the phase detector.