公开(公告)号：EP4385944A1

公开(公告)日：2024-06-19

申请号：EP22213368.8

申请日：2022-12-14

申请人： Imec VZW

发明人： Derakhshandeh, Jaber ,  Beyne, Eric

IPC分类号： B81B7/00 ,  B81C1/00 ,  B81C3/00 ,  H01L23/00

CPC分类号： H10N69/00 ,  H01L24/80 ,  H01L2224/8089520130101 ,  H01L2224/8089620130101 ,  H01L2224/0814520130101 ,  H01L24/08 ,  H01L2224/0805820130101 ,  H01L2224/0805320130101 ,  H01L2224/8036520130101 ,  B81C1/00095 ,  B81C2203/03620130101 ,  B81C1/00269 ,  B81C2203/03520130101

摘要： A first and second substrate (24,25) are bonded to each other to form a 3D assembly of micro-electronic components. Both substrates comprise a plurality of first cavities (17) open to the respective bonding surfaces (30) and at least one substrate comprises a second cavity (10) that is larger than the first cavities in terms of its in-plane dimensions, and possibly also in terms of its depth. Prior to bonding, an electrically conductive layer (16) is produced conformally on each substrate. Said layer is patterned in the large cavity or cavities (10) and in said large cavity or cavities a micro-electronic device or a portion thereof (11) is fabricated. Thereafter, the bonding surfaces are planarized, removing the conformal layer (16) from said bonding surfaces (30), after which the substrates are bonded to form the assembly, wherein the first cavities of both substrates are brought into mutual contact to form an electrical connection. Possibly, the first cavities (17) may be filled with a contact material (33) prior to the planarization step. Any device in the large cavities may be contacted through suitable connection means such as TSV connections (4,5) or back end of line interconnect levels.