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1.发明公开Clocking mechanism for multiple overlapped dynamic programmable logic arrays used in a digital control unit 失效数字控制单元中使用的多重可动态可编程逻辑阵列的时钟机制
公开(公告)号：EP0087010A3
公开(公告)日：1985-05-02
申请号：EP83100922
申请日：1983-02-01
CPC分类号： H03K5/15013 , G06F9/223
摘要： A clocking mechanism is provided for multiple overlapped dynamic programmable logic arrays which are used in a digital control unit wherein a sequence of control words are used to produce successive groups of control point signals. Such a control unit includes a plurality of dynamic programmable logic arrays (24-29) for individually producing different ones of the control words. Each such control word includes a strobe field which is coded to identify a programmable logic array other than the one which produced it. The control unit also includes control circuitry (30, 31, 35, 37, 43, 45) responsive to the control words for producing the control point signals for successive machine control cycles. The control circuitry includes circuitry (37, 45) responsive to the strobe field in each control word for producing a strobe signal (Sl, S2, SA, SB, SC or SD) for selecting the next programmable logic array (24-29) to supply a control word to the control circuitry. This control unit further includes clocking circuitry (60) responsive to the strobe signals (S1, S2, SA, etc.) produced by the control circuitry for producing clocking signals (PC1-PC9) for the dynamic programmable logic arrays (24-29). Such clocking circuitry includes only combinatorial logic circuitry for producing the clocking signals.
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公开(公告)号：EP0087874A3
公开(公告)日：1984-09-05
申请号：EP83300686
申请日：1983-02-11
申请人： SPERRY CORPORATION
CPC分类号： G01S7/282
摘要： In one embodiment the invention provides a radar trigger and pretrigger generator which determines the inherent component time delay through the radar modulator and transmitter (10) during a first cycle of operation. During the next cycle of operation, a pretrigger pulse is generated after a time corresponding to the previously measured delay and a trigger pulse is generated after a time corresponding to an operator selectable delay. The trigger pulse is used to trigger the radar modulator (10) which, in effect, permits the operator to control the elapsed time between the pretrigger pulse and the transmitter firing in a fashion which is completely independent of circuit delay variances through the radar modulator and transmitter.
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公开(公告)号：EP0148364A3
公开(公告)日：1986-11-20
申请号：EP84113527
申请日：1984-11-09
申请人： NEC CORPORATION
发明人： Fukuzo, Yukio
CPC分类号： H03K17/223 , H03K5/15
摘要： A timing signal generator which can operate stably even when, or directly after, a power supply is switched on. The generator is of the type having a first delay circuit for generating a first timing signal in response to said input control signal and a second delay circuit for generating a second timing signal in response to the first timing signal, and is featured by a first transistor connected between the output of the first delay circuit and a voltage terminal with a gate connected to the input of the first delay circuit and a second transistor connected to the output of the second delay circuit and the voltage terminal with a gate connected to receive the first timing signal.
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公开(公告)号：EP0097857A3
公开(公告)日：1985-03-13
申请号：EP83105702
申请日：1983-06-10
发明人： Freeman, Leo Boyes
CPC分类号： H03K5/02 , H03K17/603 , H03K19/0826
摘要： 57 Disclosed in a high performance current switch push-pull driver circuit. A first output of the current switch (T1, T2) is direct coupled to the push-pull driver (T5, T6) while the second output of the current switch is coupled to the push-pull driver by means of an emitter follower (T3) and current mirror (TM). Emitter followers (T3, T4) connected to the current switch (T1, T2) provide a first pair of true/ complement outputs (OUT1, OUT1) while push-pull drivers provide a second set of true/complementary outputs (OUT2, OUT2) having a higher drive capability. The current mirror (TM) is biased near its turn on potential providing current control switching of the current mode transistor and the push-pull driver transistor with which it is coupled. The circuit is greatly tolerant for varying load conditions, is protected against short circuit and power supply failures and has means for three state operation.
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公开(公告)号：EP0120702A3
公开(公告)日：1987-10-07
申请号：EP84302066
申请日：1984-03-27
发明人： Werking, Paul M.
CPC分类号： H03K5/1502 , G06F1/04 , H03K23/667
摘要： A programmable high resolution timing system includes a selectable modulus prescaler counter (16). In one embodiment a high frequency clock (14) is coupled to a prescaler counter (16) which provides an output signal (T A /T M ) every predetermined number of clock pulses. The prescaler (16) is coupled to a period counter (18) which provides a period signal (To) after a predetermined number of prescaler output signal pulses. The prescaler (16) and period counter (18) are coupled to a memory (32) which stores data corresponding to the selected modulus of the prescaler (16) and the number of counts by which the period counter (18) output signal is to be delayed. The period resolution is thus made substantially equal to the resolution of the high frequency clock (14) by varying the prescaler (16) modulus at programmable intervals.
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公开(公告)号：EP0103404A3
公开(公告)日：1985-04-03
申请号：EP83304638
申请日：1983-08-11
申请人： XEROX CORPORATION
CPC分类号： H03L7/0805 , H03K3/0315 , H03K5/15 , H03L7/0891 , H03L7/0995
摘要： A self-calibrated clock and timing signal generator provides reliable and continuous arbitrary digital waveforms of preselectable edge resolution. The generator comprises a multistage means (16) to produce a time-delayed signal of preselectable edge resolution and having a plurality of series-connected delay stages (6Q). The delays per stage are substantially identical so that the selection of any one of the outlets is representative of a predetermined amount of delay provided to an input signal to the multistage means. Calibrating means is integrally included to develop a control signal which is coupled to each of the stages of the multistage means to continuously maintain the predetermined amount of delay per stage. In the embodiment described, the calibrating means takes the form of an automatic frequency control (AFC) loop (12) wherein the frequency of a voltage controlled oscillator (VCO) (18) is regulated to be equal to that of a reference frequency. The VCO comprises a plurality of series-connected delay stages (30). The control voltage is applied to each stage to control the period or frequency of the VCO. The control voltage developed to adjust the VCO frequency is also employed to regulate the delay of the stages (60) comprising the multistage means. The stages of the delay line are identical in construction to the stages of the VCO.
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公开(公告)号：EP0056468A3
公开(公告)日：1983-02-02
申请号：EP81110494
申请日：1981-12-16
申请人： Hewlett-Packard GmbH
发明人： Becker, Josef
CPC分类号： H03K5/151 , H03K5/15006
摘要： Bei einer Schaltung zur Erzeugung von Impulsen bzw. logischen Signalen mit variablen Zustandspeglen, mit einer Umschalteinrichtung zum abwechselnden Aufschalten von den Zustandspegeln entsprechenden variablen Spannungs quellen auf den Ausgang der Schaltung weist die Umschalt einrichtung eine Diodenbrücke in Konfiguration einer Graetz Schaltung auf, deren gleiche Diodenelektroden zusammen fassenden Eckpunkte mit je einer der den Zustandspegeln entsprechenden Spannungsquellen verbunden sind und deren ungleiche Diodenelektroden zusammenfassenden Eckpunkte mit je einem von zwei komplementären Ausgän gen und mit je einer von zwei gleichen. aber entgegengesetzt gepolten Feststromquellen verbunden sind. Diese Fest stromquellen sind entsprechend einem Steuersignal umpol bar. Die den Zustandspegeln entsprechenden Spannungs quellen enthalten Operationsverstärker, in deren Rückkop plungszweigen je eine weitere mit den Dioden der Dioden brücke gleichartige Diode liegt, denen der gleiche Strom wie der der Feststromquellen eingeprägt ist und die so gepolt sind, daß der Einfluß der Spannungsabfalle in der Dioden brucke auf die Zustandspegel am Ausgang kompensiert wird.
摘要翻译： 在用于产生具有可变状态电平的脉冲或逻辑信号的电路中，包括用于将对应于状态电平的可变电压源交替地连接到电路的输出的转换开关装置，转换装置表现出二极管桥 在桥式整流电路的结构中，其组合相同的二极管电极的角点连接到对应于状态电平的一个电压源，并且将其组合不相等的二极管电极的角点连接到每个 的两个互补输出和两个相同但相反极化的固定电流源中的一个。 这些固定电流源的极性可以根据控制信号而改变。 对应于状态电平的电压源包含反馈支路中的运算放大器，其中一个另外的二极管（其中的每一个与二极管电桥的二极管相同），其中与固定电流源相同的电流是 并且以这样的方式极化，使得二极管电桥中的电压降的影响被补偿到输出端的状态电平。
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8.发明公开Apparatus and method for producing signals related in phase to a clock signal 失效用于产生与时钟信号相关的信号的装置和方法
公开(公告)号：EP0219604A3
公开(公告)日：1988-08-24
申请号：EP86107714
申请日：1986-06-06
发明人： Spencer, John R.
CPC分类号： H03K5/1504
摘要： An apparatus and method are described for generating a plurality of clock edges from a reference clock signal. The clock edges which are generated are locked in phase with the reference clock signal. The edges may be at any integral or non-integral multiple of the reference clock frequency.
摘要翻译： 描述了用于从参考时钟信号产生多个时钟边沿的装置和方法。 产生的时钟边沿与参考时钟信号锁相。 边缘可以是参考时钟频率的任何整数或非整数倍。
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9.发明公开Circuit for speeding up transfers of charges in programmable logic array structures 失效在可编程逻辑阵列结构中加快电费转移的电路
公开(公告)号：EP0105088A3
公开(公告)日：1985-03-13
申请号：EP83105931
申请日：1983-06-16
IPC分类号： H03K19/177 , H03K19/094 , H03K05/15
CPC分类号： H03K19/1772 , H03K19/096
摘要： @ Circuit for speeding up transfers of charges in a Programmed Logic Array structure, formed by FET devices (3) in serially chained charge transfer circuits, comprising a level shifting circuit (21) integrated into bit partitioning stages of the structure, for reducing voltage swings in the outputs of those stages and thereby reducing spurious couplings at the inputs of the AND array chains (24) as well as decreasing operational delays of the latter stage, discrete capacitance, (29), added at the output end of the OR array stage (10) for sustaining and reinforcing charge conditions accumulated in that stage prior to readout of that stage, and a source of time related clocking functions (Cp1-Cv3) coupled to stages of the modified structures, with the timing relationship selected so as to reduce operational delays of the entire structure while improving its integrity of operation.
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10.发明公开Input signal responsive pulse generating and biasing circuit for integrated circuits 失效集成电路的输入信号响应脉冲发生和偏置电路
公开(公告)号：EP0084146A3
公开(公告)日：1984-10-03
申请号：EP82111812
申请日：1982-12-20
摘要： A signal generating circuit for an integrated circuit device responsive to first (CS) and second (DATA IN) externally applied input signals occurring at a predetermined time interval In which the performance of a first input signal responsive circuit (12) is made to vary inversely with respect to the performance of other internal signal generating circuits (10,18, TC) such that internally generated signals will occur at a predetermined time with respect to the external input signals regardless of the influence of variable parameters. Power dissipation of the first input signal responsive circuit also varies inversely with respect to that of other circuits present on the integrated circuit device so that total power dissipation is minimized.
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