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    PROGRAMMABLE POWER FOR A MEMORY INTERFACE
    4.
    发明公开
    PROGRAMMABLE POWER FOR A MEMORY INTERFACE 审中-公开
    PROGRAMMERBARE LEISTUNGFÜREINE SPEICHERSCHNITTSTELLE

    公开(公告)号：EP3152762A1

    公开(公告)日：2017-04-12

    申请号：EP15725168.7

    申请日：2015-05-11

    申请人： Qualcomm Incorporated

    发明人： DIFFENDERFER, Jan Christian ,  CHENG, Yuehchun Claire

    IPC分类号： G11C7/10 ,  G11C7/22 ,  H03L7/08 ,  H03L7/081

    CPC分类号： G11C11/4076 ,  G11C7/1066 ,  G11C7/1093 ,  H03L7/08 ,  H03L7/0805 ,  H03L7/0812

    摘要： Systems and methods for delay control are described herein. In one embodiment, a delay system comprises a first delay circuit configured to provide a voltage bias to a second delay circuit, wherein the voltage bias controls a delay of the second delay circuit, and to update the voltage bias at an update rate. The delay system also comprises an update controller configured to adjust the update rate of the first delay circuit. For example, the update controller may adjust the update rate based on timing requirements of a memory interface incorporating the delay system. The update rate may be reduced when the timing requirements are more relaxed to reduce power, and may be increased when the timing requirements are tighter.

    摘要翻译： 本文描述了用于延迟控制的系统和方法。 在一个实施例中，延迟系统包括被配置为向第二延迟电路提供电压偏置的第一延迟电路，其中所述电压偏压控制所述第二延迟电路的延迟，并以更新速率更新所述电压偏置。 延迟系统还包括被配置为调整第一延迟电路的更新速率的更新控制器。 例如，更新控制器可以基于结合延迟系统的存储器接口的定时要求来调整更新速率。 当定时要求更放松以减少功率时，可以减少更新速率，并且当定时要求更紧时可能会增加更新速率。

    METHOD AND APPARATUS FOR IMPLEMENTING CLOCK HOLDOVER
    7.
    发明公开
    METHOD AND APPARATUS FOR IMPLEMENTING CLOCK HOLDOVER 有权
    方法和设备实现时钟保持时间

    公开(公告)号：EP2976851A1

    公开(公告)日：2016-01-27

    申请号：EP13878651.2

    申请日：2013-03-21

    申请人： Telefonaktiebolaget L M Ericsson (Publ)

    发明人： ZHU, Kai

    IPC分类号： H04L7/00

    CPC分类号： H04L7/033 ,  H03B5/32 ,  H03L7/0805 ,  H03L7/085 ,  H03L7/087 ,  H03L7/093 ,  H03L7/0992 ,  H03L7/14 ,  H04J3/0688

    摘要： The embodiments disclose a method and apparatus for implementing the clock holdover in the communication system. The apparatus receives an external source clock and outputs an output clock, and comprises a first phase-locked circuit and a second phase-locked circuit. The first phase-locked circuit is configured for taking the external source clock and a first output clock as input and outputting an intermediate clock, the first output clock is outputted by the second phase-locked circuit and fed back to the first phase-locked circuit. The first phase-locked circuit includes a first digital oscillator, and the first digital oscillator is configured to take the first output clock as a working clock to generate the intermediate clock. The second phase-locked circuit is configured for taking the intermediate clock and a local clock fed by a local oscillator as input, and outputting a second output clock.

    Programmable slew rate phase locked loop
    8.
    发明公开
    Programmable slew rate phase locked loop 有权
    Programmierbare Anstiegsgeschwindigkeits-Phasenregelschleife

    公开(公告)号：EP2860873A1

    公开(公告)日：2015-04-15

    申请号：EP14187063.4

    申请日：2014-09-30

    申请人： Thomas & Betts International, LLC

    发明人： Walraven, Justin

    IPC分类号： H03L7/07 ,  H02J9/06

    CPC分类号： H03L7/0805 ,  H02J9/062 ,  H02J2009/068 ,  H03L7/07 ,  H03L7/095 ,  H03L2207/14

    摘要： A system includes a first phase-locked loop (PLL) circuit, a slew rate limiter and a second PLL. The first PLL is configured to receive an input signal, generate a first output identifying a frequency associated with the input signal, and generate a second output identifying phase information associated with the input signal. The slew rate limiter is configured to receive the first output from the first PLL, determine whether the frequency of the first output is changing at greater than a predetermined rate, and generate a first signal indicating whether the frequency is changing at greater than the predetermined rate. The second PLL is configured to receive the first signal from the slew rate limiter, receive the second output from the first PLL, and generate an output signal identifying an angle or phase information based on the first signal and the second output.

    摘要翻译： 系统包括第一锁相环（PLL）电路，转换速率限制器和第二PLL。 第一PLL被配置为接收输入信号，产生识别与输入信号相关联的频率的第一输出，以及产生识别与输入信号相关联的相位信息的第二输出。 转换速率限制器被配置为从第一PLL接收第一输出，确定第一输出的频率是否以大于预定速率变化，并且产生指示频率是否大于预定速率的第一信号 。 第二PLL被配置为从转换速率限制器接收第一信号，从第一PLL接收第二输出，并且基于第一信号和第二输出生成识别角度或相位信息的输出信号。

    SUPPLY-REGULATED VCO ARCHITECTURE
    10.
    发明公开
    SUPPLY-REGULATED VCO ARCHITECTURE 审中-公开
    SUPPLY REGULATED体结构的一种压控振荡器

    公开(公告)号：EP2695299A1

    公开(公告)日：2014-02-12

    申请号：EP12714194.3

    申请日：2012-04-06

    申请人： Qualcomm Incorporated

    发明人： RAGHUNATHAN, Ashwin ,  PEDRALI-NOY, Marzio ,  WADHWA, Sameer

    IPC分类号： H03L7/099 ,  H03L7/24

    CPC分类号： H03L7/0995 ,  H03L7/0805 ,  H03L7/099 ,  H03L7/24

    摘要： A supply-regulated VCO exhibits reduced or no supply sensitivity peaking. The VCO includes an oscillator whose supply current is regulated to control the oscillating frequency of the oscillator. A VCO input signal controls the supply current so that there is a relationship between the input signal and the oscillator output frequency. Power supply noise that might otherwise affect oscillator operation is shunted from a supply current input lead of the oscillator to ground by a bypass capacitor. In one example, an auxiliary circuit supplies an auxiliary supply current to the oscillator, thereby reducing the amount of supply current a supply regulation control loop circuit must supply. In another example, a supply regulation control loop circuit supplies a control current to a main oscillator, but the bypass capacitor is not coupled to this oscillator but rather is coupled to a slave oscillator that is injection locked to the main oscillator.