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    Type checking in Java computing environments
    91.
    发明公开
    Type checking in Java computing environments 审中-公开
    在Javarechnerumgebungen的Typenkontrolle

    公开(公告)号：EP1310865A3

    公开(公告)日：2006-04-12

    申请号：EP02257366.1

    申请日：2002-10-23

    Applicant: SUN MICROSYSTEMS, INC.

    Inventor： Sokolov, Stephan

    IPC: G06F9/44 ,  G06F9/445

    CPC classification number: G06F9/44589 ,  G06F9/4492

    Abstract: Techniques for type checking in Java computing environments are disclosed. As will be appreciated, the techniques can be used by a Java virtual machine to efficiently perform type checking. In one embodiment, a Java class hierarchy is implemented in an internal class representation. The Java class hierarchy represents the hierarchical relationship of the parent classes for the Java class. The Java class hierarchy can be implemented, for example, as an array of class references. The array of class references can be used to efficiently perform type checking in Java computing environments. As a result, the performance of Java virtual machines, especially those operating with limited resources, can be significantly enhanced.

    TRUNKING SUPPORT IN A HIGH PERFORMANCE NETWORK DEVICE
    92.
    发明授权
    TRUNKING SUPPORT IN A HIGH PERFORMANCE NETWORK DEVICE 失效
    VERBINDINGSUNTERSTÜTZUNGIN A高性能的网络设备

    公开(公告)号：EP1002402B1

    公开(公告)日：2006-04-05

    申请号：EP98934183.9

    申请日：1998-06-25

    Applicant: SUN MICROSYSTEMS, INC.

    Inventor： MULLER, Shimon ,  HENDEL, Ariel

    IPC: H04L12/56

    CPC classification number: H04L12/4633

    Abstract: A method and apparatus for providing trunking support in a network device (201) is provided. The network device includes at least one port that is configured to be included in a trunk and a memory for storing a forwarding database (240). The forwarding database includes entries containing therein forwarding information for a subset of network addresses. The network device further includes a learning circuit (260) coupled to the trunked port and the memory. The learning circuit is configured to modify the forwarding database to reflect an association between the trunked port and a first address contained within a packet received by the trunked port. If the trunk is of a first type, the learning circuit updates the forwarding database based upon a trunk designator corresponding to the trunk, otherwise the learning circuit updates the forwarding data base based upon a port designator corresponding to the trunked port.

    Method and apparatus for reporting data transfer between hardware and software
    93.
    发明公开
    Method and apparatus for reporting data transfer between hardware and software 失效
    为硬件和软件之间的数据传输的通知的方法和装置

    公开(公告)号：EP0752664A3

    公开(公告)日：2006-04-05

    申请号：EP96110406.4

    申请日：1996-06-27

    Applicant: SUN MICROSYSTEMS, INC.

    Inventor： Oskouy, Rasoul M.

    IPC: G06F13/12 ,  G06F5/06

    CPC classification number: H04L29/06 ,  G06F5/06 ,  H04L69/32

    Abstract: A method and apparatus of reporting the status of data transfer between software and hardware in a computer system is disclosed. Software provides empty descriptors to the hardware for posting completion updates of transfers. More particularly, the software provides the number of the last available descriptor to a first storage field in a storage location which is accessible to the hardware. The hardware accounts for the number of the descriptors it has used for reporting completion updates by posting the number of used descriptors to a second storage field in the storage location. To determine if more descriptors are available, the hardware compares the contents of the first storage field to that of the second storage field. If the contents of the first and second storage fields are equal, the hardware has reached the last descriptor in the completion ring. If the fields are not equal, one or more descriptors are available for the hardware to use.

    SYSTEM AND METHOD FOR PROVIDING MASTER AND SLAVE PHASE-ALIGNED CLOCKS
    98.
    发明授权
    SYSTEM AND METHOD FOR PROVIDING MASTER AND SLAVE PHASE-ALIGNED CLOCKS 有权
    系统和方法用于提供相平衡Master和Slave时钟信号

    公开(公告)号：EP1179236B1

    公开(公告)日：2006-03-15

    申请号：EP00930771.1

    申请日：2000-05-16

    Applicant: SUN MICROSYSTEMS, INC.

    Inventor： DOBLAR, Drew, G.

    IPC: H04J3/06 ,  H04L7/033

    CPC classification number: G06F11/1604 ,  G06F1/04 ,  G06F11/20

    Abstract: A system and method for providing master and slave phase-aligned clocks. Upon a failure of a master clock signal, the system switches over to a slave clock signal in phase alignment with the master clock signal. The master clock signal is from a first clock source, while the slave clock signal is from a second clock source. The second clock source comprises a phase locked loop (PLL) including a switch, which is coupled to selectively provide the control signal to a voltage controlled oscillator (VCO). The switch may also provide a reference control voltage to the VCO. The first clock source may be on a first clock board, and the second clock source may be on a second clock board. The clock boards are preferably hot swappable. The first clock board may be removed from the system, such as upon a failure, and a third clock board placed in the system. The second clock board is switched from being the slave clock source to the master clock source, while the third clock board is configured to operate as the slave clock source. The method provides a first clock signal as a master clock signal. A second clock signal is provided as a slave clock signal, with the slave clock signal phase aligned with the master clock signal. Upon a failure of either the master clock signal or the slave clock signal, a user is notified of the failure. Upon the failure of the first clock signal, the second clock signal is switched in place of the first clock signal as the master clock signal. Clock switching is automatic and does not interrupt or interfere with operation of the computer system.

    METHOD AND APPARATUS IN A PACKET ROUTING SWITCH FOR CONTROLLING ACCESS AT DIFFERENT DATA RATES TO A SHARED MEMORY
    99.
    发明公开
    METHOD AND APPARATUS IN A PACKET ROUTING SWITCH FOR CONTROLLING ACCESS AT DIFFERENT DATA RATES TO A SHARED MEMORY 失效
    方法和设备以PAKETENLEITWEGLENKUNGSSCHALTER来访问一款常用的存储器不同的数据速率税

    公开(公告)号：EP0993680A4

    公开(公告)日：2006-03-15

    申请号：EP98934172

    申请日：1998-06-24

    Applicant: SUN MICROSYSTEMS INC

    Inventor： MULLER SHIMON ,  PHAM BINH ,  BERG CURT

    IPC: G06F13/14 ,  H01J13/00 ,  G06F13/16 ,  G06F13/362 ,  G06F15/173

    CPC classification number: G06F13/1689

    Abstract: A method and apparatus for controlling access to a shared memory in a network system is described. The apparatus includes at least one fast port interface circuit, each comprising a fast input port interface configured to sequentially receive data, address, and command information from a network client at a first data rate in segments of a first width. Each fast input port interface comprises a fast interface register configured to temporarily store the data and address information. Each fast input port interface further comprises a command decode circuit configured to receive the command information and, in response, sequentially store the segments of data and address information in the fast interface register until the fast interface register is full, the fast interface register further configured to be read out in parallel to the shared memory. The apparatus also includes at least one slow port interface circuit, each configured to receive data, address, and command information from a network client at a second data rate in segments of the first width and transmit the data, address, and command information to a storage circuit that is shared among the slow port interface circuits. The shared storage circuit comprises a plurality of slow interface registers, wherein the segments of data are sequentially stored in one of the slow interface registers at the same time the contents of another slow interface register are read out in parallel to the shared memory.

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