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    SPECIAL ADDRESS GENERATION ARRANGEMENT.
    91.
    发明公开
    SPECIAL ADDRESS GENERATION ARRANGEMENT. 失效
    特殊的地址生成装置。

    公开(公告)号：EP0034180A4

    公开(公告)日：1982-06-18

    申请号：EP80901823

    申请日：1981-03-09

    申请人： WESTERN ELECTRIC CO

    发明人： HUANG VICTOR KUO-LIANG

    IPC分类号： G06F9/34 ,  G06F3/00 ,  G06F9/345 ,  G06F12/04 ,  G06F9/32

    CPC分类号： G06F9/345 ,  G06F12/04

    摘要： In the microcomputer and computer system field, there are arrangements, such as direct memory access circuits, which automatically generate a sequence of addresses in response to an initial address. The sequence of consecutive addresses is terminated by decrementing to zero a number representing the number of consecutive addresses required. This method for terminating the sequence requires attention of a programmer to enter the correct data for terminating the sequence of addresses. The disclosed arrangement (45, 61, 62, 99, 102) generates a sequence of addresses in response to an initial address and disables generation of the sequence of addresses in response to a control signal (LAST NIB) produced from at least a portion of the initial address at the conclusion of generation of a predetermined number of sequential addresses, the predetermined number being decoded from the initial address.

    STORAGE DEVICE OPERATING IN ZONE UNIT AND DATA PROCESSING SYSTEM INCLUDING THE SAME
    94.
    发明公开
    STORAGE DEVICE OPERATING IN ZONE UNIT AND DATA PROCESSING SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：EP4180970A1

    公开(公告)日：2023-05-17

    申请号：EP22206069.1

    申请日：2022-11-08

    申请人： Samsung Electronics Co., Ltd.

    发明人： HWANG, Jooyoung

    IPC分类号： G06F12/02 ,  G06F12/04 ,  G06F3/06

    摘要： A storage device includes a memory device including a plurality of memory blocks, and a memory controller. The memory controller is configured to control a memory operation performed on the memory device by dividing the plurality of memory blocks into a plurality of superblocks. The memory controller is further configured to write a first compressed chunk generated by compressing a first chunk including data requested by a host to be written to a first superblock selected based on a first logical address received from the host among the plurality of superblocks, and generate a location-related offset of the first compressed chunk in the first superblock.

    PROCESSOR INSTRUCTIONS FOR DATA COMPRESSION AND DECOMPRESSION
    95.
    发明公开
    PROCESSOR INSTRUCTIONS FOR DATA COMPRESSION AND DECOMPRESSION 审中-公开

    公开(公告)号：EP4020172A1

    公开(公告)日：2022-06-29

    申请号：EP21197313.6

    申请日：2021-09-17

    申请人： INTEL Corporation

    发明人： Wang, Zhe ,  Alameldeen, Alaa R. ,  Hughes, Christopher J.

    IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/0811 ,  G06F12/04 ,  G06F12/084 ,  G06F12/0886

    摘要： A processor that includes compression instructions to compress multiple adjacent data blocks of uncompressed read-only data stored in memory into one compressed read-only data block and store the compressed read-only data block in multiple adjacent blocks in the memory is provided. During execution of an application to operate on the read-only data, one of the multiple adjacent blocks storing the compressed read-only block is read from memory, stored in a prefetch buffer and decompressed in the memory controller. In response to a subsequent request during execution of the application for an adjacent data block in the compressed read-only data block, the uncompressed adjacent block is read directly from the prefetch buffer.