公开(公告)号：EP4441616A1

公开(公告)日：2024-10-09

申请号：EP22769458.5

申请日：2022-08-22

Applicant: Advanced Micro Devices, Inc.

Inventor： PUNNIYAMURTHY, Kishore ,  SEYEDZADEHDELCHEH, SeyedMohammad ,  BLAGODUROV, Sergey ,  DASIKA, Ganesh ,  KOTRA, Jagadish

IPC: G06F12/0855 ,  G06F12/0888 ,  G06F12/0895 ,  G06F12/0811

CPC classification number: G06F12/0811 ,  G06F12/0895 ,  G06F2212/50720130101 ,  G06F2212/102420130101 ,  G06F12/0888 ,  G06F12/0859

公开(公告)号：EP3391227B1

公开(公告)日：2024-09-11

申请号：EP16876201.1

申请日：2016-09-20

IPC: G06F12/084

CPC classification number: G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0846 ,  G06F2212/101620130101 ,  G06F2212/104420130101 ,  G06F2212/50220130101 ,  G06F2212/60120130101

公开(公告)号：EP3974968B1

公开(公告)日：2024-09-04

申请号：EP21192702.5

申请日：2020-03-14

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F12/0862 ,  G06F2212/602820130101 ,  G06F2212/602620130101 ,  G06F9/383 ,  G06F2212/30220130101 ,  G06F2212/254220130101 ,  G06F2212/65220130101 ,  G06F12/128 ,  G06F12/12 ,  G06F12/0893 ,  G06F12/0804 ,  G06F2212/60120130101 ,  G06F2212/60820130101 ,  G06F15/173 ,  G06F12/0215 ,  G06F2212/102420130101 ,  G06F12/0607 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/5066 ,  G06F7/58 ,  G06F12/0811 ,  G06F12/0875 ,  G06F12/0895 ,  G06F2212/40120130101 ,  G06F2212/45520130101 ,  G06F9/30036 ,  G06F9/3004 ,  G06F12/0866 ,  G06F16/24569 ,  G06F2212/101620130101

公开(公告)号：EP4409419A1

公开(公告)日：2024-08-07

申请号：EP22877093.9

申请日：2022-08-24

Applicant: Advanced Micro Devices, Inc.

Inventor： MOYER, Paul J.

IPC: G06F12/0891

CPC classification number: G06F12/0815 ,  G06F12/0811 ,  G06F2212/102420130101 ,  G06F2212/100820130101 ,  G06F12/0891 ,  G06F9/3842 ,  G06F9/38585

公开(公告)号：EP4407471A1

公开(公告)日：2024-07-31

申请号：EP24153943.6

申请日：2024-01-25

Applicant: VMware LLC

Inventor： Nowatzyk, Andreas Georg ,  Subrahmanyam, Pratap ,  Akkawi, Isam Wadih ,  Nayak, Adarsh Seethanadi ,  Dua, Nishchay

IPC: G06F12/0811 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0897

CPC classification number: G06F12/0897 ,  G06F12/0888 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0811 ,  G06F2212/101620130101 ,  G06F2212/20520130101 ,  G06F2212/60120130101

Abstract: Techniques for implementing a hardware-based cache controller in, e.g., a tiered memory computer system are provided. In one set of embodiments, the cache controller can flexibly operate in a number of different modes that aid the OS/hypervisor of the computer system in managing and optimizing its use of the system's memory tiers. In another set of embodiments, the cache controller can implement a hardware architecture that enables it to significantly reduce the probability of tag collisions, decouple cache capacity management from cache lookup and allocation, and handle multiple concurrent cache transactions.

公开(公告)号：EP4325352A3

公开(公告)日：2024-06-19

申请号：EP24150660.9

申请日：2016-05-26

Applicant: Intel Corporation

Inventor： Shanbhogue, Vedvyas ,  Brandt, Jason W. ,  Sahita, Ravi L. ,  Huntley, Barry E. ,  Patel, Baiju V.

IPC: G06F9/30 ,  G06F21/52 ,  G06F12/14 ,  G06F9/38

CPC classification number: G06F21/52 ,  G06F9/3861 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/30134 ,  G06F9/3806 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/1063 ,  G06F12/1081 ,  G06F12/109 ,  G06F12/1491 ,  G06F2212/105220130101 ,  G06F2212/15120130101 ,  G06F2212/65120130101 ,  G06F2212/65720130101 ,  G06F9/30076 ,  G06F12/0811

Abstract: Embodiments of the subject disclosure provide a processor and a system. The processor comprises: a shadow stack pointer, SSP, register to store a current SSP to identify a top of a current shadow stack; a decode unit to decode a restore shadow stack pointer instruction, the restore shadow stack pointer instruction to indicate a source operand that is to have a first SSP, the first SSP to identify a top of a first shadow stack; and an execution unit coupled with the decode unit, the execution unit, in response to the restore shadow stack pointer instruction, to: perform a plurality of security checks, including to determine whether a value derived from the first SSP is compatible with a value accessed from the first shadow stack; cause an exception, if at least one of the security checks fails; and restore an SSP to the SSP register to switch from the current shadow stack to the first shadow stack, if all of the security checks succeed.

公开(公告)号：EP3485382B1

公开(公告)日：2024-05-01

申请号：EP17828472.5

申请日：2017-07-13

IPC: G06F12/0897 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/0895

CPC classification number: G06F12/0866 ,  G06F12/0895 ,  G06F12/0804 ,  G06F12/0897 ,  G06F2212/101620130101 ,  G06F2212/102820130101 ,  G06F12/0811 ,  G06F12/128 ,  Y02D10/00

公开(公告)号：EP3391227A1

公开(公告)日：2018-10-24

申请号：EP16876201.1

申请日：2016-09-20

Applicant: Advanced Micro Devices, Inc.

Inventor： LOH, Gabriel, H.

IPC: G06F12/0811 ,  G06F12/0846 ,  G06F12/0871

CPC classification number: G06F12/0897 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/0895 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/502 ,  G06F2212/601 ,  G06F2212/604

Abstract: Systems, apparatuses, and methods for implementing a hybrid cache. A processor may include a hybrid L2/L3 cache which allows the processor to dynamically adjust a size of the L2 cache and a size of the L3 cache. In some embodiments, the processor may be a multi-core processor and there may be a single cache partitioned into a logical L2 cache and a logical L3 cache for use by the cores. In one embodiment, the processor may track the cache hit rates of the logical L2 and L3 caches and adjust the sizes of the logical L2 and L3 cache based on the cache hit rates. In another embodiment, the processor may adjust the sizes of the logical L2 and L3 caches based on which application is currently being executed by the processor.

公开(公告)号：EP3385847A1

公开(公告)日：2018-10-10

申请号：EP18160824.1

申请日：2018-03-08

Applicant: INTEL Corporation

Inventor： RAY, Joydeep ,  KOKER, Altug ,  VALERIO, James A. ,  PUFFER, David ,  APPU, Abhishek R. ,  JUNKINS, Stephen

IPC: G06F12/0831 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0888 ,  G06T1/20

CPC classification number: G06T1/20 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0888 ,  G06F2212/1024 ,  G06F2212/302 ,  G06F2212/621 ,  G06T1/60

Abstract: One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.

公开(公告)号：EP3379420A1

公开(公告)日：2018-09-26

申请号：EP18155593.9

申请日：2018-02-07

Applicant: Intel Corporation

Inventor： CHEN, Wei ,  AGARWAL, Rajat ,  LING, Jing ,  LIU, Daniel W.

IPC: G06F12/0866

CPC classification number: G06F12/0808 ,  G06F1/3287 ,  G06F3/0685 ,  G06F12/0638 ,  G06F12/0811 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/12 ,  G06F12/128 ,  G06F2212/205 ,  G06F2212/283 ,  G06F2212/621

Abstract: Provided are an apparatus, system, and method to flush modified data from a first memory to a persistent second memory. A first memory controller coupled to the first memory includes at least one RAS controller to read a range of addresses in the first memory. In response to receiving a command from the power control unit, the at least one RAS controller is invoked to read data from at least one range of addresses specified for the RAS controller from the first memory. A second memory controller transfers data read from the first memory determined to be modified to the second memory. The first memory controller sends a signal to the power control unit to indicate that the modified data in the range of addresses specified for the RAS controller was flushed to the second memory in response to the RAS controller completing reading the range of addresses.