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公开(公告)号：EP1317073B1
公开(公告)日：2005-01-12
申请号：EP02102634.9
申请日：2002-11-25
CPC分类号： H04N21/4383 , H03D7/163 , H03J1/0083 , H03J5/246 , H03L7/22 , H04B1/26 , H04N21/2383 , H04N21/4382
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公开(公告)号：EP1353187A3
公开(公告)日：2004-12-08
申请号：EP03100868.3
申请日：2003-04-02
发明人： BEECH, Clive, David
IPC分类号： G01R31/316 , G01R31/26 , G01R31/28
CPC分类号： H01L22/34 , G01R31/2621 , G01R31/2831 , G01R31/2884 , H01L2924/0002 , H01L2924/00
摘要： A test structure (10) is provided for allowing a parametric test system, for example towards the end of a production line at a foundry, to measure the junction leakage of a semiconductor device such as an integrated circuit. The structure is formed as part of the device and comprises a MOSFET (3) whose source and drain are provided with connections (5 and 7) which are accessible to the tester for biasing the device and measuring the drain current. A capacitor (1) is connected between the gate of the MOSFET (3) and another connection (4) allowing the tester to supply various voltages to the connection (4). A junction diode (2) is connected between the gate of the MOSFET (3) and the body terminal and connection (6). During testing, the parametric tester supplies a voltage to the connection (4) to allow the capacitor 1 to be charged via the forward-biased diode (2). The connection (4) is then connected to another voltage such that the diode (2) becomes reverse-biased and its leakage current discharges the capacitor (1) so that the voltage on the gate of the MOSFET (3) falls. The drain current thus falls and the junction leakage through the diode (2) can be determined from the rate of change of the drain current and knowledge of the transfer characteristic of the MOSFET (3) and the capacitance of the capacitor (1).
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公开(公告)号：EP1455473A2
公开(公告)日：2004-09-08
申请号：EP04270001.3
申请日：2004-03-01
发明人： Scott, Martin, Raymond , Frost, Timothy, Michael, Edmund , Floyd, Geoffrey, Edward , Crowle, Martin
CPC分类号： H04J3/0632 , H04J3/0664
摘要： A method of synchronising first and second clocks coupled respectively to ingress and egress interfaces 6,7 of a packet network 1, the method comprising calculating a minimum packet Transit Time over the network 1 in each of successive time intervals, and varying the frequency of the second clock so as to track variations in the minimum packet Transit Time.
摘要翻译： 一种将分别耦合到分组网络（1）的入口和出口接口（6,7）的第一和第二时钟同步的方法，所述方法包括在每个连续的时间间隔中计算网络（1）上的最小分组传输时间， 并且改变第二时钟的频率，以便跟踪最小分组传送时间中的变化。
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公开(公告)号：EP1351304A3
公开(公告)日：2004-07-28
申请号：EP03100866.7
申请日：2003-04-02
IPC分类号： H01L27/08
CPC分类号： H01L27/08
摘要： An integrated circuit capacitor comprises: at least first, second and third conducting plates, the first conducting plate being positioned between the second and third plates; a first dielectric layer positioned between the first and third conducting plates; and a second dielectric layer positioned between the first and second conducting plates, wherein a portion, being an "overlap portion", of the second conducting plate extends beyond the edge of the first conducting plate and towards the third conducting plate, and the capacitor is arranged so that the electrical breakdown voltage between said overlap portion and the third conducting plate is lower than the electrical breakdown voltage between the first and second conducting plates.
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公开(公告)号：EP1388942A3
公开(公告)日：2004-05-12
申请号：EP03102462.3
申请日：2003-08-07
IPC分类号： H03M1/12
CPC分类号： H04L27/0002 , H04L27/2647
摘要： In-phase and quadrature baseband analog signals are supplied from a tuner front end (1-7) to respective sample and hold circuits (10, 11) which sample their input signals at different times. The resulting samples are converted by a single ADC (13) and the I or Q digital samples are supplied to an interpolator (20-26). The interpolator performs interpolation on (in this case) the Q digital samples to obtain further samples at the same sampling points as the I signal. The resulting samples are supplied to a digital demodulator (28).
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公开(公告)号：EP1414238A2
公开(公告)日：2004-04-28
申请号：EP03103573.6
申请日：2003-09-26
发明人： Cuthberson, Scot
IPC分类号： H04N5/64
CPC分类号： H04N5/64 , H04N5/4401 , H04N21/4135 , H04N21/414 , H04N21/426
摘要： A digital television converter (1) is provided, for example for performing all of the functions of a set top box for receiving digital terrestrial or satellite television broadcast signals. The converter (1) comprises a SCART connector (2) for mating with a mating connector (28) on a television apparatus, such as a television receiver (21) or a VCR (22), which is incapable of reception of digital television broadcasts. This connection provides electrical contact with the apparatus (21) and provides mechanical support for the converter (1). The converter also comprises a tuner (12) which selects and demodulates a television channel for reception and supplies to the connector (2) signals in a form suitable for use by the television apparatus (21). A connector rear housing (3) completes the enclosure for the converter (1) containing the tuner (12).
摘要翻译： 转换器具有连接到设置在电视机中的配合连接器的周边连接器。 提供在转换器中的调谐器通过选择和解调所需的电视频道来向连接器提供音频和视频信号。 转换器具有形成外壳以便支撑连接器和调谐器的后壳体。
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公开(公告)号：EP1369992A2
公开(公告)日：2003-12-10
申请号：EP03101305.5
申请日：2003-05-12
IPC分类号： H03F3/45
CPC分类号： H03F3/45511 , H03F3/45089 , H03F2200/294 , H03F2200/372
摘要： An amplifier, for example for use as an LNA of a radio frequency tuner, comprises a differential amplifying stage (1-5) provided with an AGC core (6-9). The output signals are formed across load resistors (10, 11) at differential outputs (OUT+, OUT-). Compensating stages (15, 16) sum the signals at the differential outputs (OUT+, OUT-) and subtract the resulting sum signal from the output signals so as to cancel the common mode signals including second order distortion products.
摘要翻译： 放大器，例如用作射频调谐器的LNA，包括具有AGC核心（6-9）的差分放大级（1-5）。 输出信号跨差分输出（OUT +，OUT-）上的负载电阻（10,11）形成。 补偿级（15,16）对差分输出（OUT +，OUT-）处的信号求和，并从输出信号中减去所得到的和信号，以消除包括二阶失真产生的共模信号。
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公开(公告)号：EP1367712A2
公开(公告)日：2003-12-03
申请号：EP03101451.7
申请日：2003-05-21
发明人： MADNI, Arshad
CPC分类号： H03F3/195 , H03F3/45085 , H03F2200/294 , H03F2200/372
摘要： An LNA for use as an input stage of a radio frequency tuner comprises an inverting amplifier stage (1) and a transconductance stage (6). The amplifier stage (1) has an input connected via an input resistance (2) to an input (3) of the amplifier and via a feedback resistance (4) to an output of the amplifier stage (1). The transconductance stage (6) passes a current through the input resistance (2) which is substantially proportional to the output voltage (Vout) of the amplifier stage (1).
摘要翻译： 用作射频调谐器的输入级的LNA包括反相放大器级（1）和跨导级（6）。 放大器级（1）具有经由输入电阻（2）连接到放大器的输入端（3）并经由反馈电阻（4）连接到放大器级（1）的输出端的输入端。 跨导级（6）使电流通过与放大级（1）的输出电压（Vout）基本成比例的输入电阻（2）。
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公开(公告)号：EP1351304A2
公开(公告)日：2003-10-08
申请号：EP03100866.7
申请日：2003-04-02
IPC分类号： H01L27/08
CPC分类号： H01L27/08
摘要： An integrated circuit capacitor comprises:
at least first, second and third conducting plates, the first conducting plate being positioned between the second and third plates;
a first dielectric layer positioned between the first and third conducting plates; and
a second dielectric layer positioned between the first and second conducting plates,
wherein a portion, being an "overlap portion", of the second conducting plate extends beyond the edge of the first conducting plate and towards the third conducting plate, and
the capacitor is arranged so that the electrical breakdown voltage between said overlap portion and the third conducting plate is lower than the electrical breakdown voltage between the first and second conducting plates.摘要翻译： 集成电路电容器包括：至少第一，第二和第三导电板，第一导电板位于第二和第三板之间; 定位在第一和第三导电板之间的第一电介质层; 以及位于所述第一和第二导电板之间的第二电介质层，其中所述第二导电板的“重叠部分”的一部分延伸超过所述第一导电板的边缘并朝向所述第三导电板，并且所述电容器 布置成使得所述重叠部分和第三导电板之间的电击穿电压低于第一和第二导电板之间的电击穿电压。
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公开(公告)号：EP0853379B1
公开(公告)日：2003-10-01
申请号：EP97310041.5
申请日：1997-12-12
CPC分类号： H03F3/26 , H03F1/22 , H03F3/343 , H03F2200/372
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