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公开(公告)号:EP4344057A1
公开(公告)日:2024-03-27
申请号:EP23198083.0
申请日:2023-09-18
申请人: Apple Inc.
发明人: SINGHAL, Nitesh , FORBES, Mark G
摘要: An electronic device may include wireless circuitry (24) with a processor (26), a transceiver (30), an antenna (42), and a front-end module (40) coupled between the transceiver (30) and the antenna (42). The front-end module (40) may include one or more power amplifiers (50) for amplifying a signal for transmission through the antenna (42). A power amplifier (50) may include multiple amplifier stages. Current sharing or reuse may occur between two amplifier stages (60, 62) in the power amplifier (50) via a current flow path between the two amplifier stages. A power supply voltage line (75) may be connected to the current flow path and may provide the downstream amplifier stage (62) with a supplemental supply current based on which the downstream amplifier stage (62) can amplify a radio-frequency signal received from the upstream amplifier stage (60).
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公开(公告)号:EP4055708A1
公开(公告)日:2022-09-14
申请号:EP19805162.5
申请日:2019-11-08
发明人: FIEDLER, Raik , PIETZSCH, Marcus
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公开(公告)号:EP3631980B1
公开(公告)日:2022-07-13
申请号:EP18728537.4
申请日:2018-05-16
发明人: MAIER, Florian , WERNER, Sergej
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公开(公告)号:EP3937376A1
公开(公告)日:2022-01-12
申请号:EP21184543.3
申请日:2021-07-08
摘要: The present invention relates to a push-pull class E amplifier. Furthermore, the present invention relates to a device comprising such a push-pull amplifier.
In the push-pull class E amplifier of the present invention a balun is realized using a multilayer printed circuit board, wherein the balanced terminals and connecting line segments are realized in an upper metal layer, whereas the unbalanced terminal and connecting line segments are realized in at least two lower metal layers.-
公开(公告)号:EP3840226A1
公开(公告)日:2021-06-23
申请号:EP19216852.4
申请日:2019-12-17
申请人: Imec VZW
发明人: Markulic, Nereo , Hershberg, Benjamin , Lagos Benites, Jorge Luis , Martens, Ewout , Craninckx, Jan
IPC分类号: H03M1/08 , G05F1/575 , H03M1/16 , H03M1/46 , H03F1/30 , H03F3/00 , H03F3/26 , H03F3/45 , H03M1/66
摘要: A device (10) for buffering a reference signal (12) is provided. The device (10) comprises a regulator circuit (11) adapted to generate at least two replicas of the reference signal as regulated output signals (12',12"). The device (10) further comprises a receiving circuit (13) adapted to receive the regulated output signals (12',12") in a switchable manner. In this context, the regulated output signals (12',12") are defined with different performance specifications.
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公开(公告)号:EP3782281A1
公开(公告)日:2021-02-24
申请号:EP18915222.6
申请日:2018-04-17
发明人: HE, Chen , WANG, Zhancang
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公开(公告)号:EP3002874B1
公开(公告)日:2018-10-17
申请号:EP15188986.2
申请日:2006-10-31
发明人: SUTARDJA, Sehat
CPC分类号: H03F3/45183 , H03F1/08 , H03F3/26 , H03F2200/36
摘要: An amplifier circuit includes a first transistor having a control terminal that receives a first amplifier input, a first terminal, and a second. The amplifier circuit includes a transimpedance amplifier having an input that communicates with the first terminal of the first transistor, and an output. The amplifier circuit includes an output amplifier having an input that communicates with the output of the transimpedance amplifier and an output.
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公开(公告)号:EP3369173A1
公开(公告)日:2018-09-05
申请号:EP16788780.1
申请日:2016-10-31
CPC分类号: H03F3/26 , H03F1/22 , H03F1/42 , H03F1/565 , H03F3/191 , H03F2200/294 , H03F2200/318 , H03F2200/391 , H03F2200/489 , H03F2200/537 , H03F2200/54 , H03F2203/45631 , H03F2203/45638 , H03F2203/45702
摘要: An amplifier for signal amplification, the amplifier comprising: a signal input arrangement; a signal output arrangement; a first transistor (Q1); a second transistor (Q2); and a third transistor (Q3), wherein: the first (Q1), second (Q2) and third (Q3) transistors are coupled to one another to form a transconductance cell, the transconductance cell is coupled to the signal input arrangement and the signal output arrangement, and the transconductance cell is operable to receive a first signal from the signal input arrangement, amplify the first signal and output an amplified first signal to the signal output arrangement. There is also disclosed a receiver incorporating the amplifier and methods of operating the amplifier.
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公开(公告)号:EP3316481A1
公开(公告)日:2018-05-02
申请号:EP16306434.8
申请日:2016-11-01
申请人: NXP USA, Inc.
CPC分类号: H03F3/45089 , G01S7/02 , H03F1/0261 , H03F3/195 , H03F3/26 , H03F3/45
摘要: A baseband amplifier circuit comprising a single-ended to differential converter followed by at least one boosted follower amplifier. The boosted follower amplifier comprises a first transconductance device arranged to control a first current between a first supply node and a first output node in response to a voltage at a first input node, a second transconductance device arranged to control a second current between the first output node and a second supply node in response to a voltage at a second input node, a third transconductance device arranged to control a third current between the first supply node and a second output node in response to a voltage at a third input node, and a fourth transconductance device arranged to control a fourth current between the second output node of the boosted follower amplifier and the second supply node in response to a voltage at a fourth input node.
摘要翻译: 基带放大器电路包括一个单端到差分转换器,后面跟着至少一个升压跟随放大器。 升压的跟随器放大器包括:第一跨导装置,被布置为响应于第一输入节点处的电压来控制第一电源节点和第一输出节点之间的第一电流;第二跨导装置,被布置为控制第一输出 响应于第二输入节点处的电压,控制第一电源节点和第二电源节点;第三跨导装置,被布置为响应于第三输入节点处的电压来控制第一电源节点和第二输出节点之间的第三电流;以及 第四跨导器件,被布置为响应于第四输入节点处的电压来控制升压跟随器放大器的第二输出节点和第二供电节点之间的第四电流。
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公开(公告)号:EP2478637B1
公开(公告)日:2018-03-07
申请号:EP10816291.8
申请日:2010-09-14
申请人: Rambus Inc.
IPC分类号: H03K17/687 , H03F3/26 , G06F13/40 , H03F3/45 , H03M1/06 , H03M1/74 , H03M1/80 , H04L25/02 , H04L25/03 , H03K19/00 , H03K19/0175 , H03M1/10
CPC分类号: H03K19/0005 , H03K19/017581 , H03M1/1061 , H03M1/745 , H04L25/0278 , H04L25/0288 , H04L25/03343
摘要: High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such "differential" or "non-uniform" sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC. In an additional set of implementations, equalization and impedance calibration functions are implemented bilaterally in respective parallel sets of driver branches, rather than in the nested "DAC within a DAC" arrangement of the hierarchical implementations. Through such bilateral arrangement, multiplication of the equalizer and calibrator quantizations is avoided, thereby lowering the total number of sub-driver slices required to meet the specified ranges and resolutions.
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