公开(公告)号：EP0630127A1

公开(公告)日：1994-12-21

申请号：EP93201758.5

申请日：1993-06-18

申请人： ALCATEL BELL Naamloze Vennootschap

发明人： De Langhe, Marc Robert François ,  Reusens, Peter Paul Frans ,  Haspeslagh, Johan Joseph Gustaaf ,  Van Hoogenbemt, Stefaan Margriet Albert

IPC分类号： H04J3/07

CPC分类号： H04J3/076

摘要： A digital phase locked loop arrangement is used in a desynchronizer demapping a plesiochronous stream from a synchronous bitstream is disclosed to remove jitter due to overhead gapping from the plesiochronous stream. To this end the part of the synchronous bitstream constituting the plesiochronous stream is written into a buffer memory (BUFF), the write address (WRADDR) of which is incremented at the rate of this plesiochronous part. The read address (RDADDR) for the buffer memory (BUFF) is derived from the write address (WRADDR) in the digital phase locked loop arrangement. Herein, a negative feedback for byte justifications in the synchronous bitstream and a positive feedback for bit justifications therein is provided so that byte justifications give rise to a lower change in the incrementing rate of the read address (RDADDR) but of longer duration, whereas bit justifications give rise to an increased change in this incrementing rate but of shorter duration.

摘要翻译： 公开了一种数字锁相环装置，用于从同步比特流中解映射同步流的去同步器，以消除由于同步流的开销间隙引起的抖动。 为此，构成同步流的同步比特流的部分被写入缓冲存储器（BUFF）中，其写入地址（WRADDR）以这个准同步部分的速率递增。 用于缓冲存储器（BUFF）的读地址（RDADDR）来自数字锁相环布置中的写地址（WRADDR）。 这里，提供了同步比特流中的字节对齐的负反馈以及其中的比特对齐的正反馈，使得字节对齐引起读地址（RDADDR）的递增速率的较低变化，但持续时间较长，而位 理由增加了这种增长率的变化，但持续时间较短。

公开(公告)号：EP0512641A1

公开(公告)日：1992-11-11

申请号：EP92201260.4

申请日：1992-05-05

申请人： ALCATEL BELL Naamloze Vennootschap

发明人： Busschaert, Hans Johan Jozef ,  Reusens, Peter Paul Frans ,  Van Camp, Ronny Maria Alfons

IPC分类号： H03M13/00

CPC分类号： H03M13/41

摘要： A decoder device (VD) used far decoding digital messages according to the Viterbi convolutional decoding algorithm. This Viterbi decoder (VD) is integrated in a portion of a single electronic chip which is included in a receiver of a handportable mobile station of a digital cellular radio system. The decoder (VD) includes a first module (VITALFA) to calculate transition probabilities for the possible state transitions between two successive states of the decoder, and a second module (VIPROB) to calculate, in function of the state transition probabilities, path probabilities for the possible paths constituted by successive state transitions and ending in each of these states, and to select the path having the highest path probability value.
The first/second module (VITALFA/VIPROB) of the device (VD) further calculates a state transition/path bit error rate which is function of the difference between the bits (softbits) received in the first module (VITALFA) and the bits (coded bits) expected for a same state transition/path respectively.

摘要翻译： 用于根据维特比卷积解码算法对数字消息进行解码的解码器装置（VD）。 该维特比解码器（VD）被集成在包括在数字蜂窝无线电系统的手持移动台的接收机中的单个电子芯片的一部分中。 解码器（VD）包括第一模块（VITALFA），用于计算解码器的两个连续状态之间的可能状态转换的转换概率，以及第二模块（VIPROB），以根据状态转移概率来计算路径概率， 可能的路径由连续的状态转换构成，并以这些状态的每一个结束，并且选择具有最高路径概率值的路径。 设备（VD）的第一/第二模块（VITALFA / VIPROB）还计算作为在第一模块（VITALFA）中接收的比特（软比特）与比特（ 编码比特）分别预期相同的状态转换/路径。

公开(公告)号：EP0462328A1

公开(公告)日：1991-12-27

申请号：EP90201602.1

申请日：1990-06-18

申请人： ALCATEL BELL Naamloze Vennootschap

发明人： Huyskens, Erik ,  Reusens, Peter Paul Frans ,  Swerts, Urbain

IPC分类号： G06F11/26 ,  G01R31/318

CPC分类号： G06F11/261 ,  G01R31/318566

摘要： A test device (TD1, SC1) operating in emulation mode for functionally replacing a processor (DSP1) of an integrated electronic chip (EC) by an emulating processor (DSP2) coupled thereto via a first scan path (SC1) built arround the processor (DSP1) and accesible via only two terminals (I, O) of the chip. The first scan path is constituted by a string of cells (CC1) connected in series between the two terminals, each cell latching a data bit normally transferred from another circuit, also built on the chip, to the processor thereof. The latched data is then serially transferred to a second scan path (SC2) similar to the first one and built arround the emulating processor. From the second scan path, the data is transmitted to the emulating processor which handles it and returns resulting data to this second scan path. This resulting data is then transferred back to the first scan path from which it is supplied to the other circuit. The transfer of data between the first and second scan paths is performed between each processing step of the emulating processor so that the test is executed in "real time".
A variant (TD2, SC1) of this test device discloses the substitution of the emulation processor (DSP2) for an observation processor (DSP3) provided with a third scan path (SC3) built arround it. This test device has a comparator (CMP) for comparing the the results of the observation processor (DSP3) and applied to the third scan path with those of the processor (DSP1) of the chip and available on the second scan path (SC2).

摘要翻译： 一种在仿真模式下工作的测试设备（TD1，SC1），用于通过在其上构建的第一扫描路径（SC1）功能地替换由集成电子芯片（EC1）的处理器（DSP1）的仿真处理器（DSP2）耦合到其上的处理器 DSP1），仅通过芯片的两个端子（I，O）可访问。 第一扫描路径由串联连接在两个终端之间的一串单元（CC1）构成，每个单元将从芯片上构建的另一个电路正常传送的数据位锁存到其处理器。 然后将锁存的数据串行地传送到与第一扫描路径类似的第二扫描路径（SC2），并建立在仿真处理器的旁边。 从第二扫描路径，将数据传送到处理它的仿真处理器，并将得到的数据返回到该第二扫描路径。 然后将所得到的数据传送回第一扫描路径，从该扫描路径将其提供给另一个电路。 在仿真处理器的每个处理步骤之间执行在第一和第二扫描路径之间的数据传送，以便以“实时”的方式执行测试。 该测试装置的一种变型（TD2，SC1）公开了仿真处理器（DSP2）代替设置有构建在其上的第三扫描路径（SC3）的观察处理器（DSP3）。 该测试装置具有比较器（CMP），用于将观察处理器（DSP3）的结果与应用于第三扫描路径的结果与芯片的处理器（DSP1）的结果进行比较，并且在第二扫描路径（SC2）上可用。

公开(公告)号：EP0257687A3

公开(公告)日：1989-12-20

申请号：EP87201504.5

申请日：1987-08-06

申请人： ALCATEL N.V.

发明人： Reusens, Peter Paul Frans

IPC分类号： H04M1/50 ,  G06F1/02

CPC分类号： H04M1/505 ,  G06F1/025

摘要： A digital transmission system including a digital signal generator (GEN) able to generate a rectangular output signal (SX2, SX2ʹ) , e.g. in the audible frequency range. The frequency and the amplitude of this output signal are respectively determined by the frequency (500/16,000 Hz) of a square wave (SQ1, SQ1ʹ) and by the duty cycle of a rectangular wave (SE0) both waves being created in the generator under control of an incoming digital word, the rectangular wave chopping the square wave. The frequency content of the spectrum of the output signal is identical to that of the square wave.

摘要翻译： 包括能够产生矩形输出信号（SX2，SX2'）的数字信号发生器（GEN）的数字传输系统， 在可听频率范围内。 该输出信号的频率和幅度分别由方波（SQ1，SQ1'）的频率（500 / 16,000Hz）和在发电机中产生的矩形波（SE0）两个波的占空比确定 控制输入​​的数字字，矩形波斩波方波。 输出信号频谱的频率成分与方波的频谱成分相同。

公开(公告)号：EP0257687A2

公开(公告)日：1988-03-02

申请号：EP87201504.5

申请日：1987-08-06

申请人： ALCATEL N.V.

发明人： Reusens, Peter Paul Frans

IPC分类号： H04M1/50 ,  G06F1/02

CPC分类号： H04M1/505 ,  G06F1/025

摘要： A digital transmission system including a digital signal generator (GEN) able to generate a rectangular output signal (SX2, SX2ʹ) , e.g. in the audible frequency range. The frequency and the amplitude of this output signal are respectively determined by the frequency (500/16,000 Hz) of a square wave (SQ1, SQ1ʹ) and by the duty cycle of a rectangular wave (SE0) both waves being created in the generator under control of an incoming digital word, the rectangular wave chopping the square wave. The frequency content of the spectrum of the output signal is identical to that of the square wave.

摘要翻译： 一种数字传输系统，包括能够生成矩形输出信号（SX2，SX2'）的数字信号发生器（GEN）。 在可听频率范围内。 该输出信号的频率和幅度分别由方波（SQ1，SQ1'）的频率（500 / 16,000Hz）和矩形波（SE0）的占空比决定，在发生器中产生两个波 在输入数字字的控制下，矩形波斩波方波。 输出信号的频谱的频率含量与方波的频率含量相同。