公开(公告)号：EP2993817A1

公开(公告)日：2016-03-09

申请号：EP14807080.8

申请日：2014-04-17

Applicant: ZTE Corporation

Inventor： LIU, Feng ,  XU, Jichao

IPC: H04J3/06

CPC classification number: H04J3/0623 ,  H04J3/076 ,  H04L5/22 ,  H04L7/0016 ,  H04L67/2842

Abstract: Disclosed are a method and a device for recovering clock data of a tributary signal in SDH, wherein the method includes that: it is to extract valid data of the signal from a time slot of each tributary in a synchronous digital hierarchy SDH frame, and store into a storage space corresponding to a time slot of each tributary in a cache; it is to recover a clock signal and a readout signal for the time slot of each tributary by means of time division multiplexing; when the readout signal for the time slot of any tributary is valid, it is to read out contents of the data from the storage space corresponding to the time slot of the tributary in the cache, and latch into a latch corresponding to the time slot; the device includes: a data extracting module, a clock recovery circuit and a data recovery module.

Abstract translation: 公开了一种用于恢复SDH中的支路信号的时钟数据的方法和设备，其中该方法包括：从同步数字层级SDH帧中的每个支路的时隙中提取信号的有效数据，并存储 进入对应于高速缓存中每个支路的时隙的存储空间; 通过时分复用来恢复每个支路的时隙的时钟信号和读出信号; 当任何支路的时隙的读出信号有效时，从与高速缓存中的支路的时隙相对应的存储空间中读出数据的内容，并锁存到对应于该时隙的锁存器中; 该装置包括：数据提取模块，时钟恢复电路和数据恢复模块。

公开(公告)号：EP2228930A3

公开(公告)日：2015-12-30

申请号：EP10155460.8

申请日：2010-03-04

Applicant: FUJITSU LIMITED

Inventor： Katagiri, Toru ,  Shioda, Masahiro

IPC: H04J3/16 ,  H04J3/07

CPC classification number: H04J3/076 ,  H04J3/1652 ,  H04J3/1664

Abstract: A frame generating apparatus accommodating a client signal in an optical data transfer unit frame with a higher bit rate than the client signal includes a deserializer, a plurality of generic mapping procedure circuits, and a serializer. The deserializer deserializes the client signal into parallel signals, the number of parallel signals corresponding to the number of tributary slots used in the optical data transfer unit frame, The plurality of generic mapping procedure circuits inserts data and stuff into a frame accommodating portion of the optical data transfer unit frame based on a difference in the bit rate between the client signal and the optical data transfer unit frame, The serializer serializes the parallel signals output from the plurality of generic mapping procedure circuits.

Abstract translation: 在具有比客户端信号更高的比特率的光数据传送单元帧中容纳客户端信号的帧生成装置包括解串器，多个通用映射过程电路和串行器。 解串器将客户端信号反序列化为并行信号，对应于在光学数据传输单元帧中使用的辅助槽的数量的并行信号的数量。多个通用映射程序电路将数据和填充插入到光学器件的框架容纳部分中 数据传输单元帧基于客户信号与光数据传送单元帧之间的比特率的差异，串行器串行化从多个通用映射过程电路输出的并行信号。

公开(公告)号：EP2348654B1

公开(公告)日：2015-04-08

申请号：EP09825930.2

申请日：2009-11-13

Applicant: Nippon Telegraph And Telephone Corporation ,  NTT Electronics Corporation

Inventor： AISAWA, Shigeki ,  TOMIZAWA, Masahito ,  MIYAMOTO, Yutaka ,  KISAKA, Yoshiaki ,  ENDO, Yasuyuki ,  MIURA, Katsuyoshi ,  TAKEI, Kazuhito

IPC: H04J3/00 ,  H04J3/07 ,  H04J3/16

CPC classification number: H04J3/1652 ,  H04J3/076 ,  H04J2203/0089

公开(公告)号：EP2348654A4

公开(公告)日：2012-07-11

申请号：EP09825930

申请日：2009-11-13

Applicant: NIPPON TELEGRAPH & TELEPHONE ,  NTT ELECTRONICS CORP

Inventor： AISAWA SHIGEKI ,  TOMIZAWA MASAHITO ,  MIYAMOTO YUTAKA ,  KISAKA YOSHIAKI ,  ENDO YASUYUKI ,  MIURA KATSUYOSHI ,  TAKEI KAZUHITO

IPC: H04J3/00 ,  H04J3/07 ,  H04J3/16

CPC classification number: H04J3/1652 ,  H04J3/076 ,  H04J2203/0089

公开(公告)号：EP2311209A1

公开(公告)日：2011-04-20

申请号：EP09772510.5

申请日：2009-07-02

Applicant: Enensys Technologies

Inventor： MARTIN, Gaël

IPC: H04J3/06 ,  H04J3/07

CPC classification number: H04J3/0632 ,  H04J3/076 ,  H04N21/23406 ,  H04N21/44004 ,  H04N21/64322 ,  H04N21/64707

Abstract: The present invention relates to a method for calculating a filtered level of padding for the input buffer of a gateway generating a data stream from a received data stream resisting the received stream jitter. The invention applies, more particularly, to a gateway receiving an MPEG (
Moving Picture Experts Group ) transport stream received according to the IP (
Internet Protocol ) protocol and re-broadcasted accordingly on an interface ASI (
Asynchronous Serial Interface ). The invention provides a method for calculating a filtered level of padding for the input buffer resisting the received stream jitter. The received stream passing through an arrival buffer, the basis of the method is a control based on the maximum buffer level evaluated over a period of time making it possible to protect itself from the effects of the jitter added to the received stream.

公开(公告)号：EP2053813A3

公开(公告)日：2010-12-08

申请号：EP08253250.8

申请日：2008-10-07

Applicant: Tektronix Inc.

Inventor： Hazzard, Shane A. ,  Tran, Que Thuy ,  Klingman, Kayla R. ,  Kelly, David L. ,  Smith, Patrick A. ,  Knierim, Daniel G.

IPC: H04L25/45 ,  H04L25/05 ,  H04L25/14 ,  H04L25/49

CPC classification number: H03M9/00 ,  H04J3/076 ,  H04L25/14 ,  H04L25/4908

Abstract: Serial data is input to a transmitter, where it is demultiplexed into a plurality of multi-bit lanes, e.g. n bits for each of N lanes. The N lanes are then encoded into characters, the encoded N lanes having m bits per lane where m>n. Bit stuffing is used to adjust the data rate and/or to insert qualifiers. The stuffed, encoded N lanes are then multiplexed into N serial lanes, which are output from the transmitter section for input to a receiver section.
In the receiver section the N lanes are deserialized, decoded and input to a word recognizer to generate a trigger event signal.

公开(公告)号：EP2124365A2

公开(公告)日：2009-11-25

申请号：EP09168627.9

申请日：2004-07-01

Applicant: Nortel Networks Limited

Inventor： Roberts, Kim B. ,  Harley, James ,  Neusy, Philippe ,  Mayer, Michael

IPC: H04J3/07 ,  H04J3/06

CPC classification number: H04J3/076

Abstract: In a method of estimating a bit rate (f1) of a digital signal conveyed through a SONET network between an originating node and a terminating node, the digital signal received by the originating node is processed to determine a result of a first function of the signal bit rate (f1) and a respective Tx local reference frequency (f2) of the originating node. A result of a second function of the Tx local reference frequency (f2) and a respective Rx local reference frequency (f3) of the terminating node is calculated. Finally, a result of a third function of the respective first and second function results is calculated, to derive an estimate of the signal bit rate (f4) relative to the Rx local reference frequency (f3).

Abstract translation: 在估计通过始发节点和终止节点之间的SONET网络传送的数字信号的比特率（f1）的方法中，由始发节点接收的数字信号被处理以确定信号的第一功能的结果 比特率（f1）和相应的Tx本地参考频率（f2）。 计算Tx本地参考频率（f2）的第二功能和终止节点的相应Rx本地参考频率（f3）的结果。 最后，计算相应的第一和第二功能结果的第三功能的结果，以导出相对于Rx本地参考频率（f3）的信号比特率（f4）的估计。

公开(公告)号：EP1675291B1

公开(公告)日：2007-04-18

申请号：EP04293123.8

申请日：2004-12-23

Applicant: Alcatel Lucent

Inventor： Wolf, Michael, Dr. ,  Thiele, Wolfgang

IPC: H04J3/07

CPC classification number: H04J3/076 ,  H03L7/0814

公开(公告)号：EP1742399A1

公开(公告)日：2007-01-10

申请号：EP06012798.2

申请日：2006-06-22

Applicant: Alcatel

Inventor： Rinaldi, Sonia ,  Razetti, Luca Gabriele ,  Gastaldello, Stefano

IPC: H04J3/07

CPC classification number: H04J3/076

Abstract: It is disclosed a mapper for mapping a tributary from a first frame into a second frame. The mapper comprises: a first register for generating a first counter which is adapted to be increased by a first value at each clock cycle of the first frame; a second register for generating a second counter which is adapted to be increased by a second value at each clock cycle of the second frame; a difference module for calculating a phase error between the first counter and the second counter; and a frame generation module, responsive to the phase error, for mapping the tributary into the second frame.

Abstract translation: 公开了一种用于将支路从第一帧映射到第二帧的映射器。 映射器包括：第一寄存器，用于产生适于在第一帧的每个时钟周期增加第一值的第一计数器; 第二寄存器，用于产生适于在第二帧的每个时钟周期增加第二值的第二计数器; 用于计算第一计数器和第二计数器之间的相位误差的差分模块; 以及响应于所述相位误差的帧生成模块，用于将所述支流映射到所述第二帧中。

公开(公告)号：EP0802643B1

公开(公告)日：2005-10-26

申请号：EP97301959.9

申请日：1997-03-21

Applicant: Marconi UK Intellectual Property Ltd

Inventor： Slater, Iain James

IPC: H04J3/07 ,  H04J3/06

CPC classification number: H04J3/076 ,  H04J3/0688 ,  H04J2203/006