公开(公告)号：EP1363458A3

公开(公告)日：2004-12-15

申请号：EP03010690.0

申请日：2003-05-13

申请人： Broadcom Corporation

发明人： MacInnis, Alexander ,  Hsiun, Vivian

IPC分类号： H04N7/26 ,  H04N7/50

CPC分类号： H04N19/00 ,  H04N19/13 ,  H04N19/174 ,  H04N19/40 ,  H04N19/61 ,  H04N19/70 ,  H04N19/85 ,  H04N19/90 ,  H04N19/91

摘要： A system and method for preprocessing a bitstream of compressed video data is presented herein. The bitstream of compressed video data can include, for example, a bitstream in accordance with the MPEG AVC standard. The bitstream is received and modified by a preprocessor to facilitate multi-row decoding. The modifications to the bitstream can include identification of starting points of macroblock rows with row headers. Additionally, multi-row decoding is further facilitated by generation of decode descriptors which indicate the starting row positions in the modified bit stream. Additionally, the modified bit stream can be formatted in accordance with a simpler coding scheme to simplify decompression.

公开(公告)号：EP1376379A2

公开(公告)日：2004-01-02

申请号：EP03007414.0

申请日：2003-04-01

申请人： Broadcom Corporation

发明人： Hsiun, Vivian ,  MacInnis, Alexander ,  Xie, Xiaodong ,  Zhong, Sheng

IPC分类号： G06F17/14

CPC分类号： G06F17/147 ,  H04N19/105 ,  H04N19/12 ,  H04N19/126 ,  H04N19/127 ,  H04N19/157 ,  H04N19/162 ,  H04N19/176 ,  H04N19/186 ,  H04N19/42 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/82

摘要： The present invention provides an apparatus and method for providing a programmable inverse discrete cosine transform, wherein the transform coefficients are loaded into a memory area of a core transform device and a variety of coding standards can thereby be handled by the same programmable core device. The core device is configured to process a certain sized data block, and the incoming source blocks are converted to conform to this size. After transformation, the proper sized result can be extracted from the transform device output. A switchable speed-up mode provides for 4-point transforms, rather than 8-point transforms. Alternatively, the invention also provides for dedicated transform hardware to be switchably used in conjunction with programmable transform hardware, depending upon the type of coding being used, and the speed of inverse transform desired.

摘要翻译： 本发明提供的装置和方法，用于提供一个可编程的逆离散余弦变换，worin变换系数被加载到核心的存储区域变换装置和各种编码标准可以由此通过相同的可编程核心设备来处理。 核心设备是被配置为处理特定大小的数据块，并输入源块转换为符合此大小。 改造后的合适尺寸的结果可以从变换装置的输出中提取。 一种可切换加速模式提供用于4点变换，而不是8点变换。 可替代地，本发明因此提供用于专用硬件变换到与可编程硬件一起使用的切换地变换，这取决于编码的类型被使用，和逆速度变换期望。

公开(公告)号：EP1365591A2

公开(公告)日：2003-11-26

申请号：EP03010691.8

申请日：2003-05-13

申请人： Broadcom Corporation

发明人： MacInnis, Alexander ,  Hsiun, Vivian

IPC分类号： H04N7/26 ,  H04N7/50

CPC分类号： H04N19/90 ,  H04N19/13 ,  H04N19/174 ,  H04N19/40 ,  H04N19/61 ,  H04N19/70 ,  H04N19/85

摘要： A system and method for transcoding an entropy-coded bitstream is presented herein. The syntax elements of the entropy-coded bitstream are decoded and transcoded into a second format. The second format can comprise a simpler format for decoding. The foregoing advantageously alleviates the processing requirements for the video decompression engine.

摘要翻译： 这里给出了用于对熵编码的比特流进行代码转换的系统和方法。 经熵编码的比特流的语法元素被解码并转码为第二格式。 第二种格式可以包含更简单的解码格式。 前述有利地减轻了视频解压缩引擎的处理要求。

公开(公告)号：EP1363458A2

公开(公告)日：2003-11-19

申请号：EP03010690.0

申请日：2003-05-13

申请人： Broadcom Corporation

发明人： MacInnis, Alexander ,  Hsiun, Vivian

IPC分类号： H04N7/26 ,  H04N7/50

CPC分类号： H04N19/00 ,  H04N19/13 ,  H04N19/174 ,  H04N19/40 ,  H04N19/61 ,  H04N19/70 ,  H04N19/85 ,  H04N19/90 ,  H04N19/91

摘要： A system and method for preprocessing a bitstream of compressed video data is presented herein. The bitstream of compressed video data can include, for example, a bitstream in accordance with the MPEG AVC standard. The bitstream is received and modified by a preprocessor to facilitate multi-row decoding. The modifications to the bitstream can include identification of starting points of macroblock rows with row headers. Additionally, multi-row decoding is further facilitated by generation of decode descriptors which indicate the starting row positions in the modified bit stream. Additionally, the modified bit stream can be formatted in accordance with a simpler coding scheme to simplify decompression.

摘要翻译： 本文给出了一种用于预处理压缩视频数据的比特流的系统和方法。 压缩视频数据的比特流可以包括例如根据MPEG AVC标准的比特流。 比特流由预处理器接收和修改以便于多行解码。 对比特流的修改可以包括用行标头识别宏块行的起点。 此外，通过产生指示修改的比特流中的起始行位置的解码描述符，进一步促进了多行解码。 此外，修改的比特流可以根据更简单的编码方案进行格式化，以简化解压缩。

公开(公告)号：EP1351513A2

公开(公告)日：2003-10-08

申请号：EP03007413.2

申请日：2003-04-01

申请人： Broadcom Corporation

发明人： Alvarez, Roberto Jose ,  MacInnis, Alexander ,  Zhong, Sheng ,  Xie, Xiaodong ,  Hsiun, Vivian

IPC分类号： H04N7/50

CPC分类号： G06F9/3861 ,  G06F9/3877 ,  H04N19/105 ,  H04N19/12 ,  H04N19/122 ,  H04N19/126 ,  H04N19/127 ,  H04N19/157 ,  H04N19/162 ,  H04N19/176 ,  H04N19/186 ,  H04N19/42 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90

摘要： A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel. The variable-length decoders operate as part of a pipeline wherein the variable-length decoders alternate, stage-by-stage, decoding macroblocks.

摘要翻译： 一种用于解码数字视频数据流的系统和方法。 在一个方面，多个硬件加速模块与核心处理器一起使用。 加速器在解码管线中操作，其中在任何给定阶段，每个加速器对视频数据的特定宏块进行操作。 在随后的流水线阶段，每个加速器对数据流中的下一个宏块进行加工，在前一阶段的另一个加速器中加工。 核心处理器在每个阶段轮询所有加速器。 当所有加速器在给定阶​​段完成任务时，核心处理器启动下一阶段。 在另一方面，采用两个可变长度解码器来同时解码视频帧的两个宏块行。 每个可变长度解码器用于对分配的行进行解码，并行并行地进行可变长度解码。 可变长度解码器作为流水线的一部分进行操作，其中可变长度解码器逐级交替解码宏块。

公开(公告)号：EP1351512A2

公开(公告)日：2003-10-08

申请号：EP03007266.4

申请日：2003-03-31

申请人： Broadcom Corporation

发明人： Maclnnis, Alexander ,  Hsiun, Vivian ,  Zhong, Sheng ,  Xie, Xiaodong ,  Alvarez, Roberto Jose

IPC分类号： H04N7/50

CPC分类号： G06F9/3861 ,  G06F9/3877 ,  H04N19/105 ,  H04N19/12 ,  H04N19/122 ,  H04N19/126 ,  H04N19/127 ,  H04N19/157 ,  H04N19/162 ,  H04N19/176 ,  H04N19/186 ,  H04N19/42 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90

摘要： System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a deblocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.

摘要翻译： 用于解码数字视频数据的系统和方法。 解码系统采用辅助核心处理器执行所选解码任务的硬件加速器。 硬件加速器可配置为支持多种现有和将来的编码/解码格式。 加速器可配置为基本上支持落入基于DCT的熵解码的块运动补偿压缩算法的一般类别中的任何现有或将来的编码/解码格式。 硬件加速器示例性地包括可编程熵解码器，逆量化模块，反离散余弦变换模块，像素滤波器，运动补偿模块和去块滤波器。 硬件加速器在解码流水线中起作用，其中在流水线中的任何给定阶段，当在给定宏块上执行给定功能时，数据流中的下一个宏块正在通过管道中的先前功能进行处理。