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1.发明公开
公开(公告)号：EP1351511A3
公开(公告)日：2005-08-10
申请号：EP03007265.6
申请日：2003-03-31
申请人： Broadcom Corporation
发明人： Maclnnis, Alexander , Hsiun, Vivian , Zhong, Sheng , Xie, Xiaodong , So, Kimming , Alvarez, Roberto Jose
IPC分类号： H04N7/50
CPC分类号： G06F9/3877 , G06F9/3861 , H04N19/105 , H04N19/12 , H04N19/122 , H04N19/126 , H04N19/127 , H04N19/13 , H04N19/157 , H04N19/162 , H04N19/176 , H04N19/186 , H04N19/42 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/70 , H04N19/82 , H04N19/90
摘要： Means of communicating between modules in a decoding system. A variable-length decoding accelerator communicates with a core decoder processor via a co-processor interface. In one embodiment, other decoding accelerators, in addition to the variable-length decoder, are adapted to provide status data indicative of their status to a co-processor status register. In another embodiment, a decoding accelerator is controlled by providing commands to the accelerator via posted write operations and polling the accelerator to determine whether the command has been performed. In still another embodiment, a first hardware accelerator communicates with a core decoder processor via a co-processor interface and other decoding accelerators, in addition to the first hardware accelerator, are adapted to provide status data indicative of their status to a co-processor status register.
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公开(公告)号：EP1351511A2
公开(公告)日：2003-10-08
申请号：EP03007265.6
申请日：2003-03-31
申请人： Broadcom Corporation
发明人： Maclnnis, Alexander , Hsiun, Vivian , Zhong, Sheng , Xie, Xiaodong , So, Kimming , Alvarez, Roberto Jose
IPC分类号： H04N7/50
CPC分类号： G06F9/3877 , G06F9/3861 , H04N19/105 , H04N19/12 , H04N19/122 , H04N19/126 , H04N19/127 , H04N19/13 , H04N19/157 , H04N19/162 , H04N19/176 , H04N19/186 , H04N19/42 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/70 , H04N19/82 , H04N19/90
摘要： Means of communicating between modules in a decoding system. A variable-length decoding accelerator communicates with a core decoder processor via a co-processor interface. In one embodiment, other decoding accelerators, in addition to the variable-length decoder, are adapted to provide status data indicative of their status to a co-processor status register. In another embodiment, a decoding accelerator is controlled by providing commands to the accelerator via posted write operations and polling the accelerator to determine whether the command has been performed. In still another embodiment, a first hardware accelerator communicates with a core decoder processor via a co-processor interface and other decoding accelerators, in addition to the first hardware accelerator, are adapted to provide status data indicative of their status to a co-processor status register.
摘要翻译： 在解码系统中的模块之间进行通信的手段。 可变长度解码加速器通过协处理器接口与核心解码器处理器进行通信。 在一个实施例中，除了可变长度解码器之外，其他解码加速器适于向协处理器状态寄存器提供表示其状态的状态数据。 在另一个实施例中，解码加速器通过经由发布的写入操作向加速器提供命令并轮询加速器来进行控制，以确定该命令是否已被执行。 在另一个实施例中，第一硬件加速器经由协处理器接口与核心解码器处理器进行通信，除了第一硬件加速器之外，其他解码加速器也适用于将指示其状态的状态数据提供给协处理器状态 寄存器。
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公开(公告)号：EP1351516A2
公开(公告)日：2003-10-08
申请号：EP03007420.7
申请日：2003-04-01
申请人： Broadcom Corporation
IPC分类号： H04N7/50
CPC分类号： G06F9/3861 , G06F9/3877 , H04N19/105 , H04N19/12 , H04N19/122 , H04N19/126 , H04N19/127 , H04N19/157 , H04N19/162 , H04N19/176 , H04N19/186 , H04N19/42 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/70 , H04N19/82 , H04N19/90
摘要： System and method of data unit management in a decoding system employing a decoding pipeline. Each incoming data unit is assigned a memory element and is stored in the assigned memory element. Each decoding module gets the data to be operated on, as well as the control data, for a given data unit from the assigned memory element. Each decoding module, after performing its decoding operations on the data unit, deposits the newly processed data back into the same memory element. In one embodiment, the assigned memory locations comprise a header portion for holding the control data corresponding to the data unit and a data portion for holding the substantive data of the data unit. The header information is written to the header portion of the assigned memory element once and accessed by the various decoding modules throughout the decoding pipeline as needed. The data portion of memory is used/shared by multiple decoding modules.
摘要翻译： 在采用解码流水线的解码系统中数据单元管理的系统和方法。 每个输入数据单元被分配一个存储元件并存储在分配的存储器元件中。 每个解码模块从分配的存储器元件获得对于给定数据单元的操作数据以及控制数据。 每个解码模块在对数据单元执行其解码操作之后将新处理的数据重新存储在相同的存储元件中。 在一个实施例中，分配的存储器位置包括用于保存对应于数据单元的控制数据的报头部分和用于保存数据单元的实质数据的数据部分。 标题信息被写入分配的存储器元件的标题部分一次，并且根据需要通过解码流水线中的各种解码模块访问。 存储器的数据部分由多个解码模块使用/共享。
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4.发明公开Inverse quantizer supporting multiple decoding standards 审中-公开反向量化仪器（Unterstützungmehrerer Dekodierungsstandards）
公开(公告)号：EP1351515A2
公开(公告)日：2003-10-08
申请号：EP03007419.9
申请日：2003-04-01
申请人： Broadcom Corporation
IPC分类号： H04N7/50
CPC分类号： H04N19/93 , H04N5/46 , H04N19/105 , H04N19/12 , H04N19/122 , H04N19/124 , H04N19/126 , H04N19/127 , H04N19/129 , H04N19/136 , H04N19/157 , H04N19/162 , H04N19/176 , H04N19/186 , H04N19/42 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/70 , H04N19/82 , H04N19/90
摘要： The present invention provides an apparatus for performing inverse quantization for multiple decoding standards, where the functional operations that comprise the inverse quantizer are modularly implemented and can be selectably performed. Each operation can be represented via a table entry in an associated memory area, with the functional operation being performed via reference to that table entry. Functional operations can be bypassed as needed if inverse quantization does not need to be performed on a set of data. Certain other processing operations can be performed between steps as needed to accommodate different coding standards. Macroblock data can be read from and written back to a common storage area, or a direct path is provided for writing the data directly to a subsequent inverse transform device.
摘要翻译： 本发明提供了一种用于对多个解码标准执行逆量化的装置，其中包括逆量化器的功能操作被模块化地实现并且可以被可选地执行。 可以通过相关联的存储器区域中的表条目来表示每个操作，其中功能操作是通过引用该表项进行的。 如果不需要对一组数据执行逆量化，则可以根据需要绕过功能操作。 可以根据需要在步骤之间执行某些其他处理操作以适应不同的编码标准。 宏块数据可以被读取并写回公共存储区域，或者提供直接路径用于将数据直接写入后续的逆变换设备。
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公开(公告)号：EP1351516A3
公开(公告)日：2005-08-03
申请号：EP03007420.7
申请日：2003-04-01
申请人： Broadcom Corporation
IPC分类号： H04N7/50
CPC分类号： G06F9/3861 , G06F9/3877 , H04N19/105 , H04N19/12 , H04N19/122 , H04N19/126 , H04N19/127 , H04N19/157 , H04N19/162 , H04N19/176 , H04N19/186 , H04N19/42 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/70 , H04N19/82 , H04N19/90
摘要： System and method of data unit management in a decoding system employing a decoding pipeline. Each incoming data unit is assigned a memory element and is stored in the assigned memory element. Each decoding module gets the data to be operated on, as well as the control data, for a given data unit from the assigned memory element. Each decoding module, after performing its decoding operations on the data unit, deposits the newly processed data back into the same memory element. In one embodiment, the assigned memory locations comprise a header portion for holding the control data corresponding to the data unit and a data portion for holding the substantive data of the data unit. The header information is written to the header portion of the assigned memory element once and accessed by the various decoding modules throughout the decoding pipeline as needed. The data portion of memory is used/shared by multiple decoding modules.
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公开(公告)号：EP1351513A3
公开(公告)日：2005-08-03
申请号：EP03007413.2
申请日：2003-04-01
申请人： Broadcom Corporation
IPC分类号： H04N7/50
CPC分类号： G06F9/3861 , G06F9/3877 , H04N19/105 , H04N19/12 , H04N19/122 , H04N19/126 , H04N19/127 , H04N19/157 , H04N19/162 , H04N19/176 , H04N19/186 , H04N19/42 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/70 , H04N19/82 , H04N19/90
摘要： A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel. The variable-length decoders operate as part of a pipeline wherein the variable-length decoders alternate, stage-by-stage, decoding macroblocks.
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公开(公告)号：EP1365591A3
公开(公告)日：2004-12-15
申请号：EP03010691.8
申请日：2003-05-13
申请人： Broadcom Corporation
发明人： MacInnis, Alexander , Hsiun, Vivian
摘要： A system and method for transcoding an entropy-coded bitstream is presented herein. The syntax elements of the entropy-coded bitstream are decoded and transcoded into a second format. The second format can comprise a simpler format for decoding. The foregoing advantageously alleviates the processing requirements for the video decompression engine.
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8.发明公开Apparatus and method to perform an inverse discrete cosine transform for multiple decoding processes 审中-公开装置和方法，用于执行逆离散余弦变换的多个解码过程的
公开(公告)号：EP1376379A3
公开(公告)日：2004-08-11
申请号：EP03007414.0
申请日：2003-04-01
申请人： Broadcom Corporation
IPC分类号： G06F17/14
CPC分类号： G06F17/147 , H04N19/105 , H04N19/12 , H04N19/126 , H04N19/127 , H04N19/157 , H04N19/162 , H04N19/176 , H04N19/186 , H04N19/42 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/82
摘要： The present invention provides an apparatus and method for providing a programmable inverse discrete cosine transform, wherein the transform coefficients are loaded into a memory area of a core transform device and a variety of coding standards can thereby be handled by the same programmable core device. The core device is configured to process a certain sized data block, and the incoming source blocks are converted to conform to this size. After transformation, the proper sized result can be extracted from the transform device output. A switchable speed-up mode provides for 4-point transforms, rather than 8-point transforms. Alternatively, the invention also provides for dedicated transform hardware to be switchably used in conjunction with programmable transform hardware, depending upon the type of coding being used, and the speed of inverse transform desired.
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公开(公告)号：EP1351515A3
公开(公告)日：2005-08-03
申请号：EP03007419.9
申请日：2003-04-01
申请人： Broadcom Corporation
IPC分类号： H04N7/50
CPC分类号： H04N19/93 , H04N5/46 , H04N19/105 , H04N19/12 , H04N19/122 , H04N19/124 , H04N19/126 , H04N19/127 , H04N19/129 , H04N19/136 , H04N19/157 , H04N19/162 , H04N19/176 , H04N19/186 , H04N19/42 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/70 , H04N19/82 , H04N19/90
摘要： The present invention provides an apparatus for performing inverse quantization for multiple decoding standards, where the functional operations that comprise the inverse quantizer are modularly implemented and can be selectably performed. Each operation can be represented via a table entry in an associated memory area, with the functional operation being performed via reference to that table entry. Functional operations can be bypassed as needed if inverse quantization does not need to be performed on a set of data. Certain other processing operations can be performed between steps as needed to accommodate different coding standards. Macroblock data can be read from and written back to a common storage area, or a direct path is provided for writing the data directly to a subsequent inverse transform device.
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公开(公告)号：EP1351512A3
公开(公告)日：2005-08-03
申请号：EP03007266.4
申请日：2003-03-31
申请人： Broadcom Corporation
IPC分类号： H04N7/50
CPC分类号： G06F9/3861 , G06F9/3877 , H04N19/105 , H04N19/12 , H04N19/122 , H04N19/126 , H04N19/127 , H04N19/157 , H04N19/162 , H04N19/176 , H04N19/186 , H04N19/42 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/70 , H04N19/82 , H04N19/90
摘要： System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a deblocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.
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