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公开(公告)号：EP0891096A2
公开(公告)日：1999-01-13
申请号：EP98202245.1
申请日：1995-07-28
IPC分类号： H04N7/26
CPC分类号： H04N21/4307 , G06F12/0207 , G06F12/04 , G06F13/16 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/91 , H04N21/4305 , H04N21/44004
摘要： A pipelined video decoder system having an input, an output and a plurality of processing stages therebetween, and receiving an input stream of encoded data comprising :
a token generator, responsive to a picture start code and to extension start code identifiers and user data in the input stream for generating a universal adaptation unit in the form of an interactive interfacing token for control and/or data functions among said processing stages, wherein said interactive interfacing token is serially transmitted through said processing stages ;
wherein a discard_user configuration bit is included in a data packet of the input stream; and a discard_extn bit is included in the [in] data packet; wherein responsive to a first condition of said discard_extn bit the token generator disregards the extension start code identifier, and responsive to a second condition of said discard_extn bit the extension start code identifier is replaced with another extension data token;
whereby extension and user data are selectively specified for the user by the processing system.摘要翻译： 一种流水线视频解码器系统，其具有输入，输出和位于其间的多个处理阶段，并且接收编码数据的输入流，所述输入流包括：令牌生成器，响应于图片开始码和扩展开始码标识符和用户数据 输入流，用于在所述处理阶段之间以用于控制和/或数据功能的交互式接口令牌的形式产生通用适配单元，其中所述交互式接口令牌通过所述处理阶段被串行地发送; 其中discard_user配置位被包括在输入流的数据分组中; 并且discard_extn位被包括在[in]数据分组中; 其中响应于所述discard_extn位的第一条件，所述令牌生成器忽略所述扩展开始代码标识符，并且响应于所述discard_extn位的第二条件，所述扩展开始代码标识符被替换为另一扩展数据令牌; 由此处理系统为用户有选择地指定扩展和用户数据。
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公开(公告)号：EP0674266A3
公开(公告)日：1997-12-03
申请号：EP95301272.1
申请日：1995-02-28
发明人： Jones, Anthony Mark , Robbins, William Philip , Patterson, Donald William Walker , Wise, Adrian Philip , Finch, Helen Rosemary , Sotheran, Martin William
IPC分类号： G06F12/02
CPC分类号： G06F13/1689 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/1673 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/91
摘要： The present invention is directed to a number of techniques for addressing and accessing memory, including accessing from RAM a number M of words that is less than the predetermined fixed burst length N of the RAM. Also disclosed is a method for accessing Dynamic Random Access Memory (DRAM) to store and retrieve data words associated with a two dimensional image, and a procedure for providing a word with fixed width, having a fixed number of bits to be used for addressing variable width data, and having a width defining field and address field, is disclosed. There is also disclosed a method to control the buffering of encoded video data organized as frames or fields. This method involves determining the picture number of each incoming decoded frame, determining the expected presentation number at any time and marking any buffer as ready when its picture number is on or after the presentation number. Finally, there is disclosed a RAM interface for connecting a bus to RAM wherein a separate address generator generates the addresses the RAM interface needs to address the RAM. The address generator communicates with the RAM interface via a two wire interface.
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公开(公告)号：EP1026600B1
公开(公告)日：2004-10-06
申请号：EP00201754.9
申请日：1995-02-28
发明人： Jones, Anthony Mark , Robbins, William Philip , Patterson, Donald William Walker , Wise, Adrian Philip , Finch, Helen Rosemary , Sotheran, Martin William
CPC分类号： G06F13/1689 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/1673 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/91
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公开(公告)号：EP0892556A3
公开(公告)日：2000-01-12
申请号：EP98202242.8
申请日：1995-07-28
CPC分类号： H04N21/4307 , G06F12/0207 , G06F12/04 , G06F13/16 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/91 , H04N21/4305 , H04N21/44004
摘要： A pipelined video decoder system having an input, an output and a plurality of processing stages therebetween, comprising : a universal adaptation unit in the form of a first interactive interfacing token for control and/or data functions among said processing stages ; a token generator, responsive to a picture start code in an input stream of encoded data for generating said first interactive interfacing token, wherein said first interactive interfacing token is serially transmitted through said processing stages ; wherein said first interactive interfacing token is a GROUP_START token for indicating a start of a group sequence; and upon generation of said GROUP_START token, said token generator generates a second interactive metamorphic interfacing token comprising a PICTURE_END token, said PICTURE_END token being serially transmitted to said processing stages before data associated with said start code is output, wherein responsive to said PICTURE_END token one of said processing stages stops processing a current picture in a first mode of operation, and said one processing stage generates a FLUSH token in a second mode of operation, wherein processing of said current picture is completed in a controlled manner.
摘要翻译： 一种流水线视频解码器系统，其具有输入，输出以及其间的多个处理级，包括：通用适配单元，其形式为用于所述处理级之间的控制和/或数据功能的第一交互式接口令牌; 令牌发生器，响应于编码数据的输入流中的图片开始代码，用于产生所述第一交互式接口令牌，其中所述第一交互式接口令牌通过所述处理级被串行地发送; 其中所述第一交互式接口令牌是用于指示组序列的开始的GROUP_START令牌; 并且在产生所述GROUP_START标记时，所述标记生成器生成包括PICTURE_END标记的第二交互变形接口标记，所述PICTURE_END标记在与所述开始代码相关联的数据被输出之前被串行地传输到所述处理阶段，其中响应于所述PICTURE_END标记一个 所述处理阶段在第一操作模式下停止处理当前画面，并且所述一个处理阶段在第二操作模式中生成FLUSH令牌，其中以受控方式完成所述当前画面的处理。
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公开(公告)号：EP0891096A3
公开(公告)日：2000-01-12
申请号：EP98202245.1
申请日：1995-07-28
CPC分类号： H04N21/4307 , G06F12/0207 , G06F12/04 , G06F13/16 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/91 , H04N21/4305 , H04N21/44004
摘要： A pipelined video decoder system having an input, an output and a plurality of processing stages therebetween, and receiving an input stream of encoded data comprising : a token generator, responsive to a picture start code and to extension start code identifiers and user data in the input stream for generating a universal adaptation unit in the form of an interactive interfacing token for control and/or data functions among said processing stages, wherein said interactive interfacing token is serially transmitted through said processing stages ; wherein a discard_user configuration bit is included in a data packet of the input stream; and a discard_extn bit is included in the [in] data packet; wherein responsive to a first condition of said discard_extn bit the token generator disregards the extension start code identifier, and responsive to a second condition of said discard_extn bit the extension start code identifier is replaced with another extension data token; whereby extension and user data are selectively specified for the user by the processing system.
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公开(公告)号：EP0891095A3
公开(公告)日：2000-01-12
申请号：EP98202244.4
申请日：1995-07-28
IPC分类号： H04N7/26
CPC分类号： H04N21/4307 , G06F12/0207 , G06F12/04 , G06F13/16 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/91 , H04N21/4305 , H04N21/44004
摘要： An apparatus for synchronizing time in a multiplexed data stream, comprising : a token source, producing a time-multiplexed stream of tokens, wherein said tokens each comprise a plurality of data words, said data words each including an extension bit which indicates a presence of additional words in said token ; a demultiplexer, accepting a stream of multiplexed data, and outputting a plurality of elementary streams of data, each said elementary stream comprising a series of access units and having a series of time stamps associated therewith ; a first circuit connected to said demultiplexer comprising a first counter ; a second circuit connected to said demultiplexer comprising a second counter ; a third circuit coupled to said first counter and said second counters for initialization of a system time therein, wherein said third circuit is responsive to a SYNC_TIME token generated in said token source ; wherein said first counter counts independently of said second counter for maintaining first and second local versions of said system time in said first circuit and said second circuit.
摘要翻译： 一种用于同步多路复用数据流中的时间的设备，包括：令牌源，产生时间多路复用的令牌流，其中所述令牌每个包括多个数据字，所述数据字每个包括扩展位，该扩展位指示存在 所述令牌中的附加词语; 解复用器，接收多路复用数据流，并输出多个基本数据流，每个所述基本流包括一系列访问单元并具有与其相关的一系列时间戳; 连接到所述解复用器的第一电路包括第一计数器; 连接到所述解复用器的第二电路包括第二计数器; 耦合到所述第一计数器和所述第二计数器用于其中的系统时间的初始化的第三电路，其中所述第三电路响应于在所述令牌源中产生的SYNC_TIME令牌; 其中所述第一计数器独立于所述第二计数器进行计数，用于在所述第一电路和所述第二电路中保持所述系统时间的第一和第二局部版本。
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公开(公告)号：EP0895166A3
公开(公告)日：1999-03-10
申请号：EP98202091.9
申请日：1995-02-28
发明人： Jones, Anthony M. , Robbins, William Philip , Patterson, Donald William Walker , Wise, Adrian Philip , Finch, Helen Rosemary , Sotheran, Martin William
IPC分类号： G06F13/42
CPC分类号： G06F13/1689 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/1673 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/91
摘要： An apparatus for connecting a bus to a RAM comprising :
a single address generator providing complete addresses that is clocked at a first clock rate; a RAM interface, comprising :
a plurality of swing buffers connected to a bus for receiving therefrom a plurality of data words from a source at a second clock rate ; a control coupled to said swing buffers a two-wire link connecting said control with said address generator wherein a request/acknowledge protocol is implemented therebetween via said link, wherein said two-wire link comprises a sender, a receiver, and a clock connected to said sender and said receiver, wherein data is transferred from said sender to said receiver upon a transition of said clock only when said sender is ready and said receiver is ready; wherein the interface is clocked at a third clock rate that is asynchronous with said first clock rate and said second clock rate, and data is transferred between a selected swing buffer and a RAM in response to a first signal that is generated by said control when said control receives an address from the address generator and said control receives a second signal from said selected swing buffer via said communication link摘要翻译： 一种用于将总线连接到RAM的设备，包括：提供以第一时钟速率计时的完整地址的单个地址发生器; RAM接口，包括：多个摆动缓冲器，连接到总线，用于以第二时钟速率从源接收来自源的多个数据字; 耦合到所述摆动缓冲器的控制器连接所述控制器和所述地址发生器的双线链路，其中经由所述链路在它们之间实现请求/确认协议，其中所述双线链路包括发送器，接收器和连接到 所述发送者和所述接收者，其中，只有当所述发送者准备好并且所述接收者准备好时，在所述时钟转换时，数据才从所述发送者传送到所述接收者; 其中所述接口以与所述第一时钟速率和所述第二时钟速率不同步的第三时钟速率被时钟控制，并且响应于所述控制器在所述第一时钟速率和所述第二时钟速率之间产生的第一信号，在选择的摆动缓冲器和RAM之间传送数据 控制器从地址发生器接收地址并且所述控制器经由所述通信链路从所述选择的摆动缓冲器接收第二信号
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公开(公告)号：EP0896474A2
公开(公告)日：1999-02-10
申请号：EP98202171.9
申请日：1995-02-28
发明人： Wise, Adrian Philip , Sotheran, Martin William , Robbins, William Philip , Finch, Helen Rosemary , Boyd, Kevin James
CPC分类号： G06F13/28 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/1673 , G06F13/1689 , H04N19/13 , H04N19/423 , H04N19/61 , H04N19/91
摘要： A system for decoding video data and having a Huffman decoder, comprising :
an index to data (ITOD) stage, having a first mode of operation wherein an index number obtained from said Huffman decoder is converted into decoded data, and a second mode of operation wherein tokens received from said Huffman decoder are ignored, said tokens comprising a plurality of data words, each said word including an extension indicator which indicates a presence or an absence of additional words in said token, a length of said token being determined by said extension indicators, whereby the length of said token can be unlimited ;
an arithmetic logic unit (ALU) ; and
a data buffering means immediately following said system,
whereby time spread for video pictures of varying data size can be controlled.-
公开(公告)号：EP0895167A2
公开(公告)日：1999-02-03
申请号：EP98202092.7
申请日：1995-02-28
发明人： Jones, Anthony M. , Robbins, William Philip , Patterson, Donald William Walker , Wise, Adrian Philip , Finch, Helen Rosemary , Sotheran, Martin William
IPC分类号： G06F13/42
CPC分类号： G06F13/1689 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/1673 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/91
摘要： A configurable RAM interface for connecting a bus to RAM comprising :
a bus configuration register for specifying a number of bits on the bus ;
means for receiving from the bus a plurality of data words comprising multiword tokens;
means for receiving from the bus a complete address associated with the plurality of data words ;
means for generating a series of addresses in RAM into which the buffered data words will be written ;
means for writing the buffered data words into RAM at the generated addresses ; and
means for buffering the received data words comprising :
at least three memory buffers for use as a swing buffer including an arrival buffer, an output buffer and at least one intermediate buffer ;
a buffer manager for allocating said buffers for reference by said means for generating a series of addresses, clearing said buffers for occupation by subsequently arriving data, and maintaining status information of said buffers, wherein said status information comprises a state VACANT, wherein one of said buffers is available, a state IN_USE, wherein said one buffer is referenced by said means for receiving from the bus an address and by said means for receiving from the bus a plurality of data words, a state FULL, wherein said one buffer is occupied by data, and a state READY; wherein said buffer manager asserts a late arrival signal indicating that a buffer in said state READY is not in synchronization with a data output rate.摘要翻译： 一种用于将总线连接到RAM的可配置RAM接口，包括：总线配置寄存器，用于指定总线上的多个位; 用于从总线接收包括多词记号的多个数据字的装置; 用于从总线接收与多个数据字相关联的完整地址的装置; 用于在RAM中产生一系列地址的装置，缓冲数据字将被写入其中; 用于在所生成的地址处将缓冲的数据字写入RAM的装置; 以及用于缓冲所接收的数据字的装置，包括：至少三个存储器缓冲器，用作包括到达缓冲器，输出缓冲器和至少一个中间缓冲器的摆动缓冲器; 缓冲器管理器，用于通过所述用于产生一系列地址的装置分配所述缓冲器以供参考，通过随后到达的数据清除所述缓冲器以用于占用，并且维持所述缓冲器的状态信息，其中所述状态信息包括状态VACANT，其中所述 缓冲器是可用的，状态IN_USE，其中所述一个缓冲器由所述用于从总线接收地址的装置以及通过所述用于从总线接收多个数据字的装置来引用，状态为FULL，其中所述一个缓冲器被 数据和状态READY; 其中所述缓冲器管理器声明延迟到达信号，所述延迟到达信号指示所述状态READY中的缓冲器不与数据输出速率同步。
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公开(公告)号：EP0891094A2
公开(公告)日：1999-01-13
申请号：EP98202243.6
申请日：1995-07-28
IPC分类号： H04N7/26
CPC分类号： H04N21/4307 , G06F12/0207 , G06F12/04 , G06F13/16 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/91 , H04N21/4305 , H04N21/44004
摘要： A parallel Huffman decoder, comprising :
an input, accepting a mixed data stream comprising Huffman coded variable length codes, fixed length codes, and data tokens, wherein all complete Huffman codes are received in a single cycle of operation ;
a selector operative on said data stream, wherein in a first mode of operation variable length codes are provided to said address lines of a Huffman Code ROM, and in a second mode of operation data tokens and a signal representative of a length of fixed length codes is output by the decoder without reference to said ROM ;
a pair of input registers for receiving Huffman coded data, both of said registers directing input in parallel to said selector ; and
a Huffman Code ROM for receiving input from said selector and another ROM table select input; said ROM providing a first decoded data output, said selector being responsive to a second output of said ROM.摘要翻译： 1.一种并行霍夫曼解码器，包括：输入端，接受包括霍夫曼编码的可变长度码，固定长度码和数据权标的混合数据流，其中所有完整的霍夫曼码在单个操作周期中被接收; 在所述数据流上操作的选择器，其中在第一操作模式中，将可变长度码提供给霍夫曼码ROM的所述地址线，并且在第二操作模式中操作数据令牌和表示固定长度码的长度的信号 由解码器输出而不参考所述ROM; 一对输入寄存器，用于接收霍夫曼编码数据，两个所述寄存器并行地将输入指向所述选择器; 和霍夫曼代码ROM，用于接收来自所述选择器的输入和另一个ROM表选择输入; 所述ROM提供第一解码数据输出，所述选择器响应于所述ROM的第二输出。
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