公开(公告)号：EP0161947A2

公开(公告)日：1985-11-21

申请号：EP85400383.7

申请日：1985-02-28

申请人： FUJITSU LIMITED

发明人： Kunitoki, Tadayoshi ,  Gotoh, Kunihiko

IPC分类号： G11C17/00 ,  G11C17/16

CPC分类号： G11C17/16

摘要： The fuse circuit comprises a fuse (F) and a transistor (Tr4) connected in series with an impedance element (Tr1, R) between a negative and a positive voltage supply sources (V ss , V DD ). A potential (Vp) is generated at the junction point between the transistor (Tr4) and the impedance element (Trl, R) and is applied to an inverter for indicating the fuse state. The impedance element including a transistor (Tr1) forms a constant-current source, and the internal resistance of transistor (Tr4) varies as a function of the fuse resistance. Due to the provision of the impedance element, a predetermined threshold resistor value can be provided which allows a correct detection of the fuse condition, even when the fuse is in "regrown fuse" or "grown-back" fuse state due to leakage between the fuse terminals after blowing of the fuse.

摘要翻译： 熔丝电路包括与负电压源和正电压源（VSS，VDD）之间的阻抗元件（Tr1，R）串联连接的熔丝（F）和晶体管（Tr4）。 在晶体管（Tr4）和阻抗元件（Tr1，R）之间的连接点处产生电位（Vp），并施加到用于指示熔丝状态的逆变器。 包括晶体管（Tr1）的阻抗元件形成恒流源，并且晶体管（Tr4）的内部电阻随着熔丝电阻的变化而变化。 由于提供了阻抗元件，所以即使当熔丝处于“再生熔丝”或“后退”熔丝状态时，也可以提供预定的阈值电阻值，这允许对熔丝状态的正确检测， 保险丝熔断后熔断器。

公开(公告)号：EP0318396B1

公开(公告)日：1995-02-22

申请号：EP88402978.6

申请日：1988-11-25

申请人： FUJITSU LIMITED

发明人： Kobayashi, Osamu ,  Gotoh, Kunihiko

IPC分类号： H03F1/30

CPC分类号： H03F1/308

公开(公告)号：EP0458659A3

公开(公告)日：1993-08-11

申请号：EP91400494.0

申请日：1991-02-22

申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

发明人： Gotoh, Kunihiko ,  Sekido, Yuuji

IPC分类号： H03M1/06 ,  G05F3/28 ,  H03M1/66 ,  G05F1/00

CPC分类号： H03M1/0604 ,  G05F3/262 ,  H03M1/662 ,  H03M1/742

摘要： A semiconductor integrated circuit device comprising a bias generating circuit having an operational amplifier connected to receive an input voltage at its inverting input terminal to produce a gate voltage, a field effect transistor having its gate connected to receive the gate voltage from said operational amplifier and its drain connected to a resistor and to a noniverting input terminal of said operational amplifier, and further field effect transistor having its gate connected to receive the gate voltage from said operational amplifier to produce a current corresponding to the input voltage, one group of current sources responsive to an output voltage of said bias generating circuit to produce a plurality of currents of an equal magnitude and one switching circuit responsive to an input digital value to selectively output the currents from said group of current sources to its common output.

公开(公告)号：EP0280123B1

公开(公告)日：1992-05-06

申请号：EP88102025.9

申请日：1988-02-11

申请人： FUJITSU LIMITED

发明人： Kobayashi, Osamu ,  Gotoh, Kunihiko

IPC分类号： H04N5/18

CPC分类号： H04N5/185

公开(公告)号：EP0257878A3

公开(公告)日：1991-01-09

申请号：EP87306975.1

申请日：1987-08-06

申请人： FUJITSU LIMITED

发明人： Kobayashi, Osamu ,  Shimizu, Yoshiaki ,  Gotoh, Kunihiko

IPC分类号： H03M1/66 ,  H03M1/10

CPC分类号： H03M1/1061 ,  H03M1/667 ,  H03M1/806

摘要： A D/A converter, especially a cyclic type D/A converter, having an error detection and correction system including: a code conversion circuit (101) for converting a binary code (C) to a multi-states code; a digital-to-analog conversion circuit (102) connected to the code conversion circuit (101) for converting the multi-states code to an analog value; a detection circuit (103) operatively connected to the digital-to-analog conversion circuit for converting the analog value to a digital code; and a control circuit (104) operatively connected to the code conversion circuit (101), digital-to analog conversion circuit (102) and detection circuit (103) for calculating a voltage difference between the analog value at a predetermined code value and another analog value adjacent to the predetermined code value, and for calculating a differential non-linearity error from the voltage difference based on the digital code, in order to obtain error and correction values of capacitors forming the digital-to-analog conversion circuit.

摘要翻译： 一种具有错误检测和纠正系统的D / A转换器，尤其是循环型D / A转换器，包括：用于将二进制码（C）转换成多状态码的码转换电路（101） 一个连接到代码转换电路（101）的数字 - 模拟转换电路（102），用于将多状态码转换成模拟值; 检测电路（103），可操作地连接到所述数模转换电路，用于将所述模拟值转换为数字码; （101），数 - 模转换电路（102）和检测电路（103），用于计算预定代码值的模拟值与另一模拟值之间的电压差的控制电路（104） 并且用于根据数字码根据电压差来计算差分非线性误差，以便获得形成数字模拟转换电路的电容器的误差和校正值。

公开(公告)号：EP0194134A3

公开(公告)日：1988-07-27

申请号：EP86301537

申请日：1986-03-05

申请人： FUJITSU LIMITED

发明人： Kousaka, Kunimitsu ,  Gotoh, Kunihiko

IPC分类号： H03K19/094

CPC分类号： H03K19/0948 ,  H03K19/018521

摘要： @ A semiconductor integrated circuit including: an inverter circuit (1) including first and second transistors (T 7 , T 8 ) of different conductivities, and a level shift circuit (2), the first transistor (T 7 ) being supplied with an input signal (IN) via the level shift circuit (2), the second transistor (T 8 ) being supplied with the input signal (IN) directly, and the level shift circuit (2) having an amount of level shift such that, when an input signal (IN) corresponding to an «H» logic level is received, the level of the input signal supplied via the level shift circuit (V A ) is shifted near to the threshold level of the first transistor (T 7 ), to ensure correct switching of the first transistor (T 7 ). The level shift circuit (2) may be formed by a level divider circuit (T 1 , T 2 , T 3 ) and a source follower circuit (T 4 , T 5 ).

摘要翻译： 一种半导体集成电路，包括：具有不同导电性的第一和第二晶体管（T7，T8）以及电平移动电路（2）的反相器电路（1），第一晶体管（T7）被提供输入信号（IN （2），第二晶体管（T8）直接被提供有输入信号（IN），并且电平移位电路（2）具有电平移位量，使得当输入信号（IN） ）被接收时，通过电平移位电路（VA）提供的输入信号的电平被移位到接近第一晶体管（T7）的阈值电平，以确保正确切换第一晶体管 （T7）。 电平移位电路（2）可以由分压器电路（T1，T2，T3）和源极跟随器电路（T4，T5）形成。

公开(公告)号：EP0193901A3

公开(公告)日：1986-11-05

申请号：EP86102660

申请日：1986-02-28

申请人： FUJITSU LIMITED

发明人： Kousaka, Kunimitsu ,  Gotoh, Kunihiko ,  Kobayashi, Osamu

IPC分类号： H03K05/24

摘要： In a comparator circuit comprising a first power supply terminal means and a second power supply terminal means, a differential stage connected between the first power supply terminal means and the second power supply terminal means, a first input signal having a reference level and a second input signal having a level which is compared with the reference level being input to each of a pair of input terminals of the differential stage, respectively, an output signal having a level which is determined in accordance with the level of the second input signal being output from an output terminal of the differential stage, and an output stage connected to the output terminal of the differential stage, through which output stage the output signal of the differential stage is amplified; a bypass circuit through which a predetermined constant current flows is connected between the output terminal of the differential stage and the second power supply terminal means. The bypass circuit may be always closed or may be closed only when the output level of the output stage has reached the predetermined value.

公开(公告)号：EP0195633A2

公开(公告)日：1986-09-24

申请号：EP86301931.1

申请日：1986-03-17

申请人： FUJITSU LIMITED

发明人： Kousaka, Kunimitsu ,  Gotoh, Kunihiko

IPC分类号： H03F3/50 ,  H03F3/343 ,  H03F3/345

CPC分类号： H03F3/505 ,  H03F3/343 ,  H03F3/345

摘要： The semiconductor integrated circuit comprises a first power supply terminal (V cc ) and a second power supply terminal; a first transistor (T 5 ) and a second transistor (T 8 ) having gates (or bases) connected in common; an input terminal (IN) and an output terminal (OUT) connected to each source (or each emitter) of the first and second transistors (T 5 ,T 8 ) respectively, an output voltage level (V out ) being obtained from the output terminal (OUT) in accordance with an input signal voltage level (V in ) supplied to the input terminal (IN); and a current mirror circuit (3) operating so that a first current flows through the first transistor (T 5 ) in proportion to a second current flowing through the second transistor (T a ), the value of the second current being determined in accordance with the output voltage level (V out ) and a value of a load (L) connected between the output terminal (OUT) and the second power supply terminal; and thereby, a voltage level supplied to the gates (or bases) of the first and second transistors (T 5 ,T 8 ) is varied in accordance with the value of the second current.
Also, the above semiconductor integrated circuit may be used as a constant current output circuit by providing an output terminal (OUT) in one of the transistors (T 9 ) comprising the current mirror circuit (3), for supplying a predetermined constant current, and connecting a variable resistor (R cnt ) instead of the above load (L).

公开(公告)号：EP0192456A2

公开(公告)日：1986-08-27

申请号：EP86301107.8

申请日：1986-02-18

申请人： FUJITSU LIMITED

发明人： Saito, Tadahiro ,  Gotoh, Kunihiko

IPC分类号： H04M1/24 ,  H04M1/50 ,  H04M1/31 ,  G01R31/28

CPC分类号： H04M1/24 ,  H04M1/312 ,  H04M1/50

摘要： In a semiconductor integrated circuit (10) comprising an internal circuit (9), an oscillating circuit (1) generating a basic clock signal for operating the internal circuit (9) when the internal circuit is operated in a usual mode, a pair of terminals (Toscin, Toscout) connected to the input side and output side of the oscillating circuit (1), respectively, an oscillator (8) being connected between the above pair of terminals (Toscin, Toscout) when the internal circuit (9) is , operated in a usual mode, a reset terminal (Treset) through which a reset signal for resetting the internal circuit is supplied from outside the integrated circuit (10) to the internal circuit, and a test circuit (3, 4, 5) for operating the internal circuit (9) in a test mode; the test circuit supplies a clock signal for testing from outside the integrated circuit to the internal circuit (9) through one of the above pair of terminals (Toscout) when signals of a predetermined level are supplied from outside of the chip to the test circuit through each of the other one of the above pair of terminals (Toscin) and the reset terminal (Treset).

摘要翻译： 在包括内部电路（9）的半导体集成电路（10）中，当内部电路以常规模式操作时，产生用于操作内部电路（9）的基本时钟信号的振荡电路（1），一对端子 （Toscin，Toscout）分别连接到振荡电路（1）的输入侧和输出侧，当内部电路（9）被操作时，连接在上述一对端子（Toscin，Toscout）之间的振荡器（8） 在通常的模式中，复位端子（Treset）通过该复位端子（Treset）将用于复位内部电路的复位信号从集成电路（10）的外部提供给内部电路;以及测试电路（3,4,5） 内部电路（9）处于测试模式; 当从芯片的外部向测试电路提供预定电平的信号时，测试电路通过上述一对端子（Toscout）中的一个将集成电路外部的测试时钟信号提供给内部电路（9） 上述一对终端（Toscin）和复位终端（Treset）中的每一个。

公开(公告)号：EP1049173A1

公开(公告)日：2000-11-02

申请号：EP00302672.1

申请日：2000-03-30

申请人： FUJITSU LIMITED

发明人： Yamaguchi, Shigeto ,  Gotoh, Kunihiko ,  Hirochi, Katsuji

IPC分类号： H01L29/06 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/28 ,  H01L21/32

CPC分类号： H01L21/823462 ,  H01L27/0629

摘要： A method is provided to manufacture a semiconductor device which is capable of using multiple (three or more) power supplies by forming gate insulating films having different thicknesses. The method has the steps of: defining first, second and third active regions (AR1-3) on a surface of a semiconductor substrate (31); forming an insulating film (32) on the surfaces of the first, second and third active regions (AR1-3); removing the insulating film (32) on the surface of the second active region (AR2); forming an insulating film (34) on the surface of the second active region (AR2) and thickening the insulating films (32a) on the surfaces of the first and third active regions (AR1, AR3); removing the insulating film (32a) on the surface of the third active region (AR3); and forming an insulating film (36) on the surface of the third active region (AR3) and thickening the insulating films (32b, 34a) on the surfaces of the first and second active regions (AR1, AR2).

摘要翻译： 提供了一种通过形成具有不同厚度的栅极绝缘膜来制造能够使用多个（三个或更多个）电源的半导体器件的方法。 该方法具有以下步骤：在半导体衬底（31）的表面上限定第一，第二和第三有源区（AR1-3）; 在所述第一，第二和第三有源区域（AR1-3）的表面上形成绝缘膜（32）; 去除第二有源区域（AR2）的表面上的绝缘膜（32）; 在所述第二有源区域（AR2）的表面上形成绝缘膜（34），并使所述第一和第三有源区域（AR1，AR3）的表面上的所述绝缘膜（32a）变厚; 去除第三有源区域（AR3）的表面上的绝缘膜（32a）; 以及在所述第三有源区域（AR3）的表面上形成绝缘膜（36），并使所述第一和第二有源区域（AR1，AR2）的表面上的所述绝缘膜（32b，34a）变厚。